User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
R
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18.2. DRAMCL—DRAM Control Low
Address offset : 03001h
Default value : 17h
Access : Read / write
Size : 8 bit
7 5 4 3 2 1 0
Reserved Paging
Mode
Control
RAS-to-
CAS
Override
CAS#
Latency
RAS#
Riming
RAS#
Precharge
Timing
Bit Description
7:5 Reserved
4 Paging Mode Control (PMC).
0 = Page Open Mode. In this mode the GMCH memory controller tends to leave pages open.
1 = Page Close Mode. In this mode The GMCH memory controller tends to leave pages closed.
3 RAS-to-CAS Override (RCO). In units of local memory clock periods. (i.e., row activate command to
read/write command)
Bit RAS#-to-CAS# delay (t
RCD
)
0 determined by CL bit (default)
1 2
2 CAS# Latency (CL). In units of local memory clock periods.
Bit CL RAS#-to-CAS# delay (t
RCD
)
0 2 2
1 3 3 (default)
1 RAS# Riming (RT). This bit controls RAS# active to precharge, and refresh to RAS# active delay (in
local memory clocks).
Bit RAS# act. To precharge (t
RAS
) Refresh to RAS# act. (t
RC
)
0 5 8
1 7 10 (default)
0 RAS# Precharge Timing (RPT). This bit controls RAS# precharge (in local memory clocks).
Bit RAS# Precharge (t
RP
)
0 2
1 3 (default)