User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
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Table 16. Overlay Register/Instruction Categories
Register/Instruction Category Mem. Address Offset Comment
Overlay 0 Register Update Address
(OV0ADD)
30000h • Used to update Overlay 0 registers.
• Provides physical memory address of
buffer area used for updating on-chip
registers
• Write of OV0ADD register causes
hardware to update on-chip registers on
next VBLANK.
Display/Overlay 0 Status Register
(DOV0STA)
30008h • Overlay Status bits
Gamma Correction (GAMMA[0:5]) 30010h–30027h • Not part of double-buffer scheme. Access
registers directly.
Overlay Register Sets
• Overlay Buffer Pointer
• Overlay Stride
• Overlay Initial Phase
• Overlay Dest. Window Position/Size
• Overlay Source Size
• Overlay Scale Factor
• Overlay Color Correction
• Overlay Destination Color Key
• Overlay Source Color Key
• Overlay Configuration
• Overlay Command
301xxh
(on chip RO regs)
Base+xxh
(Mem Buffer regs)
• “xx” indicates a particular register address.
• On-chip registers are not directly writeable.
 Registers are double buffered
(buffer in memory and on-chip
registers).
 Software sets up buffer in
memory.
 Software writes to OV0ADD
Register which provides memory buffer
address location and causes hardware
to read memory buffer and update on-
chip registers during next VBLANK.
• On-chip registers can be read through
Debug read path. See OV0ADD register
description
Overlay Flip Instruction NA • This instruction invokes the Overlay
register update.