User's Manual

Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0
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12. 2D Instructions
This chapter contains the 2D graphics controller instructions. For each instruction the format specifies
the functionality of a field. When an instruction does not require a field, it is ignored. All registers can
only be written through instructions. No program I/O writing of the BLT registers is allowed.
12.1. BLTs To and From Cacheable Memory
The blitter can be used to transfer data from cacheable memory to graphics memory and vice versa using
the blitter command packets. The source or destination operands in these packets can be steered towards
cacheable memory.
Patterns may be used with the source. The driver is required to flush the drawing pipelines before and
after each copy command targeting cacheable memory. In addition, the driver is required to turn
arbitration off if this command is used from the low priority ring buffer. An example sequence from the
low priority ring buffer is:
ARB_OFF, FLUSH, SCB, .........,FLUSH, SCB, FLUSH, ARB_ON. Where all Source copy blits (SCBs)
use cacheable memory.
Either the source or destination surface can be in cacheable memory. Both Source and Dest surfaces in
cacheable memory, as part of the same blit operation is not allowed. In either case the surface address
programmed in this instruction must be in graphics address space. The GTT must be programmed to set
up a scatter-gather translation from graphics memory pages to physical pages in cacheable memory. A
surface that is being mapped to cacheable space must not be tiled or fenced.
A further restriction is that the source data must be the same pixel width as the destination. The only
function, which is allowed, is color copies with a positive destination pitch and direction. The source
operand can be either sign to allow mirroring in the vertical direction. An immediate source operand is
not allowed.
12.2. BLT Engine Instructions
The following instructions are directed to the BLT Engine. The Instruction Target field is used as an
opcode by the BLT Engine state machine to qualify the control bits, which are relevant for executing the
instruction. The description for each DWord and bit field is contained in the BLT Engine Instruction
Definition section. Each DWord in a packet has a corresponding Instruction Definition description where
the details of the operation of the function are described.
Note: All reserved fields must be programmed to 0s.