R Intel® 815 Chipset: Graphics Controller Programmer’s Reference Manual (PRM) July 2000 Order Number: 298237-001
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Contents 1. Introduction ................................................................................................................................ 15 1.1. 1.2. 2. ® Intel 815 Chipset Overview....................................................................................................... 17 2.1. 2.2. 2.3. 3. Terminology...................................................................................................................
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 6.3. 7. Source Data .................................................................................................58 6.2.2. 6.2.3. Monochrome Source Data...........................................................................59 6.2.4. Pattern Data.................................................................................................60 6.2.5. Destination Data .............................................................................
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.5. 9.6. 9.4.5. AR12Memory Plane Enable Register .................................................... 104 9.4.6. AR13Horizontal Pixel Panning Register ................................................ 105 9.4.7. AR14Color Select Register.................................................................... 106 VGA Color Palette Registers ....................................................................................... 106 9.5.1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 10. Programming Interface .............................................................................................................141 10.1. 10.2. 10.3. 10.4. 10.5. 11. Instruction Parser Instructions ..................................................................................................153 11.1. 11.2. 12. Introduction ..................................................................................................................
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 12.3. 13. TEXT_Immediate_BLT ............................................................................. 169 12.2.6. 12.2.7. COLOR_BLT ............................................................................................. 170 12.2.8. PAT_BLT................................................................................................... 171 12.2.9. MONO_PAT_BLT ...............................................................................
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 13.9. 13.10. 13.11. 13.12. 13.13. 13.14. 13.15. 13.16. 13.17. 13.18. 13.19. 13.20. 13.21. 13.22. 13.23. 13.24. 13.25. 13.26. 13.27. 13.28. 13.29. 14. Clock Control Registers ............................................................................................................257 14.1. 14.2. 14.3. 14.4. 14.5. 14.6. 14.7. 15. Programming Notes.....................................................................................................
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 15.5. 16. 15.4.3.3. HORZ_PH—Horizontal Phase Register ....................................... 279 15.4.3.4. INIT_PH—Initial Phase Register .................................................. 280 15.4.4. Overlay Destination Window Position/Size Registers ............................... 281 15.4.4.1. DWINPOS—Destination Window Position Register..................... 281 15.4.4.2. DWINSZ—Destination Window Size Register .............................
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R ISR—Interrupt Status Register ..................................................................326 Error Identity, Mask and Status Registers .................................................327 ® 16.2.6.1. Page Table Error handling in Intel 815 Chipset...........................327 16.2.6.2. Resetting the Page Table Error.....................................................328 16.2.6.3. EIR—Error Identity Register......................................
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25 Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34 Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. 12 Supported System Bus and System Memory Bus Frequencies.........................22 Memory-Mapped Registers ................................................................................32 I/O and Memory Register Map .................................................................
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Revision History Rev. 1.
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Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 1. Introduction The Intelâ 815 chipset is a highly flexible chipset designed to extend from the basic graphics/multimedia PC platform up to the mainstream performance desktop platform. The chipset consists of an Intel® 82815 chipset Graphics and Memory Controller Hub (GMCH), an I/O Controller Hub (ICH) for the I/O subsystem, and a Firmware* Hub (FWH).
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 1.2. Term Description MCH The Memory Controller Hub component that contains the processor interface, DRAM controller, and AGP interface. The MCH communicates with the ICH over a proprietary interconnect called the hub interface (previously known as HubLink). The MCH was called the North Bridge (NB) in previous chip sets. MCH will be used to refer to non-graphics portion of the GMCH. MM Memory Mapped address space. MMIO Memory Mapped I/O space.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 2. Intel® 815 Chipset Overview The chipset consists of an Intel® 82815 chipset Graphics and Memory Controller Hub (GMCH), an I/O Controller Hub (ICH) for the I/O subsystem, and a Firmware* Hub (FWH). The GMCH integrates a system memory SDRAM controller that supports a 64-bit 100/133 MHz SDRAM array.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Figure 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R • Support for a single processor configuration • 64-bit AGTL+ based System Bus Interface at 66/100/133 MHz • 32-bit Host Address Support • 64-bit System Memory Interface with optimized support for SDRAM at 100/133 MHz • Integrated 2D & 3D Graphics Engines • Integrated H/W Motion Compensation Engine • Integrated 230 MHz DAC • Integrated Digital Video Out Port • 133 MHz Display Cache • AGP 1X/2X/4X Controller Figure 2.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R • 370-pin socket (PGA370). The PGA370 is a zero insertion force (ZIF) socket that a processor in the FC-PGA package will use to interface with a system board. 2.2.2. System Memory Interface The GMCH integrates a system memory controller that supports a 64-bit 100/133 MHz SDRAM array. The only DRAM type supported is industry standard Synchronous DRAM (SDRAM). The SDRAM controller interface is fully configurable through a set of control registers.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Display Cache Interface The GMCH supports a Display Cache SDRAM controller with a 32-bit 133 MHz SDRAM array. The DRAM type supported is industry standard Synchronous DRAM (SDRAM) like that of the system memory. The local memory SDRAM controller interface is fully configurable through a set of control registers. 2.2.4. Hub Interface The hub interface is a private interconnect between the GMCH and the ICH. 2.2.5.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 2.2.6. System Clocking The Intel® 82815 chipset GMCH has a new type of clocking architecture. It has integrated SDRAM buffers that run at either 100 or 133 MHz, independent of the system bus frequency. See table below for supported system bus and system memory bus frequencies. The system bus frequency is selectable between 66 MHz, 100 MHz or 133 MHz. The GMCH uses a copy of the USB clock as the DOT Clock input for the graphics pixel clock PLL.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Figure 3.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R To support a PCI graphics device, the Intel® 815 chipset simply passes all of that device’s cycles to the hub interface as it would for any other PCI device.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 2.3.1.2. System Startup The Intel® 815 chipset has multiple possible device modes. The selection of which mode will be autodetected is represented in the following flow chart. The software requirements for implementing this high level flow are detailed in the next section. Multi-monitor configurations are not addressed, as that is a function of the operating system when supported.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 2.3.1.3. Software Start-Up Sequence The following sequence of events will occur during the initialization of an Intel® 815 chipset-based system: 1. The ICH asserts PCIRST# either in response to an initial assertion of PWROK or a write to an I/O Port. 2. System BIOS runs basic POST code to test the processor. 3.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 14. During PCI enumeration, the system BIOS will identify and initialize the primary display device. The selection of the primary display device is typically OEM dependent. An OEM may use a BIOS setup question to allow the system user to select the primary display device. Intel recommends the system BIOS to give preference to the higher performance display device when performing an “auto-selection” of the primary display device.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 3. 2.3.1.4. After the conclusion of the graphics driver startup code the internal graphics functions will be ready for run-time activity and commands can be written into the ring buffer. Switching Device modes Under normal conditions, the GMCH Device Mode will be switched at most once: from AGP to Internal Graphics mode (via APCONT[0]) when no external AGP graphics device is present.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 3. System Address Map This chapter provides address maps of the graphics controller (GC) I/O and memory-mapped registers. Individual register bit field descriptions are provided in the following chapters. Note that PCI configuration register descriptions are not covered in this document. For details on PCI configuration registers, refer to the Intel® 815 Chipset: 82815 Graphics and Memory Controller (GMCH) EDS.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 3.1. Memory and I/O Space Registers This section provides a high-level register map (register groupings per function). The memory and I/O maps for the GC registers are shown in the following figure. The VGA and Extended VGA registers can be accessed via standard VGA I/O locations as well as via memory-mapped locations. In addition, the memory map contains allocation ranges for various functions.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R • VGA and Extended VGA Control Registers (00000h− −00FFFh). These registers are located in both I/O space and memory space. The VGA and Extended VGA registers contain the following register sets: General Control/Status, Sequencer (SRxx), Graphics Controller (GRxx), Attribute Controller (ARxx), VGA Color Palette, and CRT Controller (CRxx) registers. Detailed bit descriptions are provided in the VGA and Extended VGA Register Chapter.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 3.2. GC Register Memory Address Map All GC registers are memory-mapped. In addition, the VGA and Extended VGA registers are I/O mapped. Table 2. Memory-Mapped Registers Address Offset 00000h−00FFFh Symbol Register Name VGA and VGA Extended Registers Access These registers are both memory and I/O mapped and are listed in the following table. Note that the I/O address and memory offset address are the same value for each register.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Table 2.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Table 2.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Table 2.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Table 2.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 3.3.1. Table 3.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 3.4. Indirect VGA and Extended VGA Register Indices Programming an index value into the appropriate SRX, GRX, ARX, or CRX register indirectly accesses the registers listed in this section. The index and data register address locations are listed in the previous section. Additional details concerning the indirect access mechanism are provided in the VGA and Extended VGA Registers Chapter (see SRxx, GRxx, ARxx or CRxx sections). Table 4.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Table 6. 2D Attribute Controller Registers (3C0h / 3C1h) Index 00h Table 7.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 3.4.1. Graphics Address Translation The Intel® 815 chipset uses a logical memory-addressing concept for accessing graphics data. The GC supports a 64-MB logical address space, where each 4-KB logical page can be mapped to a physical memory page in System RAM, PCI Memory, or an optional Display Cache memory. This mapping is performed through the use of a Graphics Translation Table (GTT). GC engines can address the full 64-MB logical address space.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Figure 8. GTT Mapping System Memory 4 GB 31 0 Graphics Translation Table (GTT) 31 0 Base + 64 MB Virtual Graphics Memory Graphics Engine Address Space 64 KB 31 0 64 MB Base + 32 MB Base 0 TOM 0 KB Optional Display Cache 4 KB GTT Maps 4KB blocks of Virtual Graphics Memory to 4 KB pages in System Memory 4 KB GTT Maps 4KB blocks of Virtual Graphics Memory to 4 KB pages in Display Cache gtt.vsd 3.4.2.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 4. Graphics Translation Table (GTT) Range Definition Address Offset: Default Value: Access: 10000h–FFFFh Page table range 64 KB aligned DWord-QWord Write Only This range defined within the graphics memory mapped register space is for the memory manager to access the graphics translation table. A page table write will invalidate that entry in internal translation table caches (TLBs).
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Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 5. Basic Initialization Procedures 5.1. Initialization Sequence The initialization of graphics driver resources can be broken down into three categories: hardware detection, frame buffer initialization, and hardware register initialization. Each category is discussed in more detail in the following sections.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Once the operating system has identified the device, it can load the appropriate driver. One of the first tasks of the driver is to make sure that the device matches the driver. Checking that the driver and device match is done in much the same way that the operating system identifies the graphics adapter. That is, the PCI VendorId and ProductId values are examined.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 5.4. Hardware Register Initialization 5.4.1. Color vs. Monochrome Monitors The mapping and initialization of some hardware registers depends in part on whether the graphics adapter is attached to a monochrome or color monitor. The following steps illustrate how to determine the type of output device attached to the graphics adapter: • Read the Miscellaneous Output Register (0x3CC).
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 5.6. Saving the Hardware State Note that the VGA register unlocking protocol must be performed in order to access some of the registers described below.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 5.7. Restoring the Hardware State The graphics adapter state should be restored by performing the following steps. Note some of the synchronization operations, especially those that ensure that the local memory is idle during the state restore. Also, much of the work involves reprogramming the registers with the values captured during the save-state operation. • Blank the screen. • Turn off DRAM refresh.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R • Other registers that should restore only certain bits from the saved-state values: Bit Blit Control MM 0x7000c Read the current value of the Bit Blit Control Register. Clear the bits pertaining to the Color Expansion Mode (bits 5:4). OR–in the saved value of the Bit Blit Control Register. Write the result back into the Bit Blit Control Register. Display Control Field MM 0x70008 Read the current value of the Display Control Register.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Watermark and Burstlength Control MM 0x20D8 Read the current value of the Watermark and Burstlength Control Register. Clear the burst length and watermark bits (bits 22:20, 17:12, 10:8 and 5:0). OR–in the saved value of the Watermark and Burstlength Control Register. Write the result back into the Watermark and Burstlength Control Register.
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Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 6. Blt Engine Programming 6.1. BLT Engine Programming Considerations 6.1.1. When the Source and Destination Locations Overlap It is possible to have BLT operations in which the locations of the source and destination data overlap. This frequently occurs in BLT operations where a user is shifting the position of a graphical item on the display by only a few pixels.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Figure 9. Source Corruption in BLT with Overlapping Source and Destination Locations (b) Source (c) (a) Destination (d) (e) (f) Source (g) (i) Destination (h) b_blt2.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R The BLT engine can alter the order in which source data is read and destination data is written when necessary to avoid source data corruption problems when the source and destination locations overlap. The command packets provide the ability to change the point at which the BLT engine begins reading and writing data from the upper left-hand corner (the usual starting point) to one of the other three corners.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R The figure below illustrates how this feature of the BLT engine can be used to perform the same BLT operation as was illustrated in the figure above, while avoiding the corruption of source data. As shown in the figure below, the BLT engine reads the source data and writes the data to the destination starting with the right-most pixel of the bottom-most line.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 6.2. Basic Graphics Data Considerations 6.2.1. Contiguous vs. Discontinuous Graphics Data Graphics data stored in memory, particularly in the frame buffer of a graphics system, has organizational characteristics that often distinguish it from other varieties of data.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Figure 13. Representation of On-Screen 6x4 Array of Pixels in the Frame Buffer (0, 0) (639, 0) 63 32 31 0 270F8h 28100h 28108h 256, 256 261, 256 270F8h 28100h 28108h 256th Scan Line 257th Scan Line 258th Scan Line 259th Scan Line 256, 259 270F8h 28100h 28108h 261, 259 270F8h 28100h 28108h Note: Drawing is not to scale (0, 479) (639, 479) b_blt6.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R If the color source data resides within the frame buffer or main memory graphics memory, then the Source Address Register, specified in the command packets is used to specify the address of the source.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R monochrome source data can be set in the source expansion foreground color register and the source expansion background color register. The BLT Engine requires that the bit alignment of each scan line’s worth of monochrome source data be specified. Each scan line’s worth of monochrome source data is word aligned, but can actually start on any bit boundary of the first byte.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Figure 15. 8bpp Pattern Data -- Occupies 64 Bytes (8 quadwords) 63 57 56 48 47 40 39 32 31 24 23 16 15 8 7 Pixel (0, 7) 0 Pixel (0, 0) 00h 08h 10h 18h 20h 28h 30h Pixel (7, 7) Pixel (7, 0) 38h b_blt9.vsd Figure 16. 16bpp Pattern Data -- Occupies 128 Bytes (16 quadwords) 63 48 47 32 31 16 15 0 Pixel (0, 0) 00h Pixel (7, 0) 08h 68h 70h Pixel (0, 7) Pixel (7, 7) 78h b_blt10.vsd Figure 17.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Figure 18. 2bpp Pattern Data -- Occupies 256 Bytes (32 quadwords) 63 48 47 32 31 16 15 Pixel (0, 0) Pixel (3, 0) 0 00h 08h 68h Pixel (4, 7) Pixel (7, 7) 70h 78h b_blt10.vsd As is shown in 24bpp pattern data figure, there are four bytes allocated for each pixel on each scan line’s worth of pattern data, which allows each scan line’s worth of 24bpp pattern data to begin on a 32-byte boundary.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 6.3. BLT Programming Examples 6.3.1. Pattern Fill -- A Very Simple BLT In this example, a rectangular area on the screen is to be filled with a color pattern stored as pattern data in off-screen memory. The screen has a resolution of 1024x768 and the graphics system has been set to a color depth of 8 bits per pixel. Figure 19.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Figure 20. Pattern Data for Example Pattern Fill BLT 63 Pattern Data (0, 0) (7, 0) (0, 7) (7, 7) (7, 0) (0, 0) 0 100000h 100008h 100010h 100018h 100020h 100028h 100030h 100038h (7, 7) (0, 7) b_blt22.vsd As shown in figure above, the pattern data occupies 64 bytes starting at address 100000h. As always, the pattern data represents an 8x8 array of pixels.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Figure 21. Results of Example Pattern Fill BLT 63 (0, 0) 128, 128 (1023, 0) 128, 128 191, 128 Scan Lines 128 Through 191 0 20080h 20088h 20090h 20098h 200A0h 200A8h 200B0h 200B8h On 128th Scan Line 2FC80h 2FC88h 2FC90h 2FC98h 2FCA0h 2FCA8h 2FCB0h 2FCB8h On 191th Scan Line (191, 128) (128, 191) 128, 191 191, 191 Note: Drawing is not to scale (0, 767) (1023, 767) (191, 191) b_blt21.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 6.3.2. Drawing Characters Using a Font Stored in System Memory In this example BLT operation, a lowercase letter “f” is to be drawn in black on a display with a gray background. The resolution of the display is 1024x768, and the graphics system has been set to a color depth of 8 bits per pixel. Figure 22.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R monochrome BLT operand following the BLT_TEXT command. The BLT engine will receive this data through the command stream and use it as the source data for this BLT operation. The BLT engine will be set to the same color depth as the graphics system 8 bits per pixel, in this case. Since the source data in this BLT operation is monochrome, color expansion must be used to convert it to an 8 bpp color depth.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R This BLT operation does not use the values in the Pattern Address Register, the Source Expansion Background Color Register, or the Source Expansion Foreground Color Register. Figure 24.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 7. Initialization Registers To function, all registers described in this section must be programmed for the Intel® 815 chipset family of products. The default states of these registers, with the exception of registers that deal with extended modes or performance enhancements, will prevent the Intel® 815 chipset family products from booting. Note: 7.1. The registers in this document are normally programmed by the video BIOS.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Bit Description 7:6 Graphics Mode Select (GMS). This field is used to enable/disable the Internal Graphics device and select the amount of Main Memory that is “Stolen” to support the Internal Graphics device in VGA (non-linear) mode only. These 2 bits only have meaning if we are not in AGP mode.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Bit Description 1 SMM Space Locked (D_LCK). When D_LCK is set to 1 then D_LCK, GMS, USMM, and the most significant bit of LSMM become read only. D_LCK can be set to 1 via a normal configuration space write but can only be cleared by a reset. The combination of D_LCK and LSMM provide convenience with security.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 7.3. Display, I/O, GPIO, Clock, LCD, and Pixel Pipeline Registers These registers are described elsewhere in this document. Refer to the appropriate sections of this PRM for detailed bit/field descriptions.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 7.4. 2D Graphics Controller Registers (3CEh / 3CFh) Refer to Chapter 9, “VGA and Extended VGA Registers” for detailed bit/field descriptions. Index 7.5. Sym Register Name 10h GR10 Address Mapping 11h GR11 Page Selector 2D CRT Controller Registers (3B4h/3D4h/3B5h/3D5h) Refer to Chapter 9, “VGA and Extended VGA Registers” for detailed bit/field descriptions.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 7.6.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
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Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 8. Frame Buffer Access The VGA frame buffer is located at A000h-BFFFh. This is the standard VGA frame buffer address. The physical location of the frame buffer is at the top of main memory. The size can either be 512 KB or 1 MB. This is selected in the SMRAM register, which is documented in the Initialization Registers section of this document.
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Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9. VGA and Extended VGA Registers This chapter describes the registers and the functional operation notations for the observable registers in the 2D section. Each register is documented and the various bit settings defined. It is important to note that not all combinations of bit settings result in functional operating modes. Note that these registers can be accessed via either I/O space or memory space.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.1.1. ST00 Input Status 0 I/O (and Memory Offset) Address: Default: Attributes: 7 6 CRT Int 5 Reserved (00) Bit 7 3C2h 00h Read Only 4 3 RGB Cmp / Sen 0 Reserved (0000) Descriptions CRT Interrupt Pending. Note that the generation of interrupts can be enabled, through bits [4,5] of the Vertical Retrace End Register (CR11).
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.1.2. ST01 Input Status 1 I/O (and Memory Offset) Address: Default: Attributes: 3BAh/3DAh 00h Read Only The address selection is dependent on CGA or MDA emulation mode as selected via the MSR register. 7 6 Reserved (0) Reserved (0) 5 Bit 4 Video Feedback 3 Vertical Retrace Reserved (as per VGA specification). Read as 0s. 6 Reserved. Read as 0. 3 1 Reserved (00) 0 Display Enable Descriptions 7 5:4 2 Video Feedback 1, 0.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.1.3. FCR Feature Control I/O (and Memory Offset) Address: Default: Attributes: 3BAh/3DAh Write; 3CAh Read 00h See Address above The address selection for reads is dependent on CGA or MDA emulation mode as selected via the MSR register. 7 4 Reserved (0000) Bit 7:4 3 3 VSYNC Control 2 0 Reserved (000) Descriptions Reserved. Read as 0. VSYNC Control. 0 = Vsync output on the VSYNC pin (default).
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.1.4. MSR Miscellaneous Output I/O (and Memory Offset) Address: Default: Attributes: 3C2h Write; 3CCh Read 00h See Address above 7 6 5 4 VSYNC Polarity HSYNC Polarity Page Select Reserved (0) Bit 7 3 2 Clock Select 1 0 A0000− BFFFFh Acc En I/O Address Descriptions CRT VSync Polarity. 0 = Positive Polarity (default). 1 = Negative Polarity. 6 CRT HSync Polarity. 0 = Positive Polarity (default).
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Table 8. 9.2. CRT Display Sync Polarities V H Display Horizontal Frequency Vertical Frequency P P >480 Line Variable Variable P P 200 Line 15.7 KHz 60 Hz N P 350 Line 21.8 KHz 60 Hz P N 400 Line 31.5 KHz 70 Hz N N 480 Line 31.5 KHz 60 Hz Sequencer Registers The sequencer registers are accessed via either I/O space or Memory space.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.2.2. SR00 Sequencer Reset I/O (and Memory Offset) Address: Default: Attributes: 3C5h(Index=00h) 00h Read/Write 7 2 Reserved (000000) Bit 7:2 1 1 0 Reserved (scratch bit) Reserved (scratch bit) Descriptions Reserved. Read as 000000. Write has no effect. Read/Write scratch bit required for VGA compatibility. Read previously written value. Write stores written value. This bit is a fully readable/writeable MMIO location in the hardware.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.2.3. SR01 Clocking Mode I/O (and Memory Offset) Address: Default: Attributes: 7 6 Reserved (00) 5 4 3 2 1 0 Screen Off Shift 4 Dot Clock Divide Shift Load Reserved (0) 8/9 Dot Clocks Bit 7:6 5 3C5h (Index=01h) 00h Read/Write Descriptions Reserved. Read as 0s. Screen Off. The display and hardware cursor will be disabled by setting the Screen Off bit.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.2.4. SR02 Plane/Map Mask I/O (and Memory Offset) Address: Default: Attributes: 7 3C5h (Index=02h) 00h Read/Write 4 Reserved Bit 3 0 Memory Planes Processor Write Access Enable. Descriptions 7:4 Reserved. Read as 0s. 3:0 Memory Planes [3:0] Processor Write Access Enable. In both the Odd/Even Mode and the Chain 4 Mode, these bits still control access to the corresponding color plane. 0 = Disable. 1 = Enable.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.2.5. SR03 Character Font I/O (and Memory Offset) Address: Default: Attributes: 7 6 Reserved (00) 5 4 Char Map A Select (bit 0) Char Map B Select (bit 0) Bit 7:6 3:2,5 1:0,4 3C5h (index=03h) 00h Read/Write 3 2 Character Map A Select (bits 2 and 1) 1 0 Character Map B Select (bits 2 and 1) Descriptions Reserved. Read as 0s. Character Map Select Bits for Character Map B.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.2.6. SR04 Memory Mode Register I/O (and Memory Offset) Address: Default: Attributes: 7 4 Reserved (0000) Bit 7:4 3 3C5h (index=04h) 00h Read/Write 3 2 1 0 Chain 4 Odd/Even Extended Memory Reserved (0) Description Reserved. Read as 0s. Chain 4 Mode. The selections made by this bit affect both processor Read and Write accesses to the frame buffer.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.2.7. SR07 Horizontal Character Counter Reset I/O (and Memory Offset) Address: Default: Attributes: 3C5h (index=07h) 00h Read/Write Writing this register with any data causes the horizontal character counter to be held in reset (the character counter output will remain 0) until a write occurs to any other sequencer register location with SRX set to an index of 0 through 6.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.3.2. GR00 Set/Reset Register I/O (and Memory Offset) Address: Default: Attributes: 7 3CFh (index=00h) 0Uh (U=Undefined) Read/Write 4 Reserved (0000) Bit 3 2 1 0 Set/Reset Plane 3 Set/Reset Plane 2 Set/Reset Plane 1 Set/Reset Plane 0 Description 7:4 Reserved. Read as 0s. 3:0 Set/Reset Plane [3:0].
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.3.4. GR02 Color Compare Register I/O (and Memory Offset) Address: Default: Attributes: 3CFh (Index=02h) 0Uh (U=Undefined) Read/Write 7 4 Reserved (0000) Bit 9.3.5. 3 2 1 0 Color Compare Plane 3 Color Compare Plane 2 Color Compare Plane 1 Color Compare Plane 0 Description 7:4 Reserved. Read as 0s. 3:0 Color Compare Plane [3:0].
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.3.6. GR04 Read Plane Select Register I/O (and Memory Offset) Address: Default: Attributes: 3CFh (Index=04h) 0Uh (U=Undefined) Read/Write 7 2 1 Reserved (000000) Bit 0 Read Plane Select Description 7:2 Reserved. Read as 0s. 1:0 Read Plane Select. These two bits select the memory plane from which the processor reads data in Read Mode 0. In Odd/Even Mode, bit 0 of this register is ignored.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Bit 6:5 Description Shift Register Control. In standard VGA modes, pixel data is transferred from the 4 graphics memory planes to the palette via a set of 4 serial output bits. These 2 bits of this register control the format in which data in the 4 memory planes is serialized for these transfers to the palette.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Bit 4 Description Odd/Even Mode. 0 = Addresses sequentially access data within a bit map, and the choice of which map is accessed is made according to the value of the Plane Mask Register (SR02). 1 = The frame buffer is mapped in such a way that the function of address bit 0 is such that even addresses select memory planes 0 and 2 and odd addresses select memory planes 1 and 3.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.3.8. GR06 Miscellaneous Register I/O (and Memory Offset) Address: Default: Attributes: 7 3CFh (Index=06h) 0Uh (U=Undefined) Read/Write 4 Reserved (0000) Bit 3 2 Memory Map Mode 1 0 Chain Odd/Even Graphics / Text Mode Description 7:4 Reserved. Read as 0s. 3:2 Memory Map Mode.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.3.9. GR07 Color Don’t Care Register I/O (and Memory Offset) Address: Default: Attributes: 3CFh (Index=07h) 0Uh (U=Undefined) Read/Write 7 4 Reserved (0000) Bit 3 2 1 0 Ignore Color Plane 3 Ignore Color Plane 2 Ignore Color Plane 1 Ignore Color Plane 0 Description 7:4 Reserved. Read as 0s. 3:0 Ignore Color Plane [3:0].
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.3.11. GR10 Address Mapping I/O (and Memory Offset) Address: Default: Attributes: 7 3CFh (Index=10h) 00h R/W 5 Reserved 4 3 2 1 0 Paging to LM VGA Buffer / Memory Map Packed Mode Enable Linear Mapping Page Mapping Bit 7:5 4 Description Reserved. Page to Local Memory Enable.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Table 9.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.3.13. GR[14:1F] Software Flags I/O (and Memory Offset) Address: Default: Attribute: Bit 7:0 100 3CFh (Index=14h-1fh) 00 R/W Description Software Flags. Used as scratch pad space in BIOS. These have no effect on H/W.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.4. Attribute Controller Registers Unlike the other sets of indexed registers, the attribute controller registers are not accessed through a scheme employing entirely separate index and data ports. I/O address 3C0h (or memory address 3C0h) is used both as the read and write for the index register, and as the write address for the data port. I/O address 3C1h (or memory address 3C1h) is the read address for the data port.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.4.2. AR[00:0F] Palette Registers [0:F] I/O (and Memory Offset) Address: Default: Attributes: 7 6 Read at 3C1h and Write at 3C0h; (index=00h-0Fh) 00UU UUUUb (U=Undefined) Read/Write 5 0 Reserved Palette Bits P[5:0] Bit Description 7:6 Reserved. Read as 0s. 5:0 Palette Bits P[5:0].
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Bit 5 Description Pixel Panning Compatibility. 0 = Scroll both the upper and lower screen regions horizontally as specified in the Pixel Panning Register (AR13). 1 = Scroll only the upper screen region horizontally as specified in the Pixel Panning Register (AR13).
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.4.4. AR11 Overscan Color Register I/O (and Memory Offset) Address: Default: Attributes: Read at 3C1h and Write at 3C0h; (index=11h) UUh (U=Undefined) Read/Write Bit 7:0 9.4.5. Description Overscan. These 8 bits select the overscan (border) color. The border color is displayed during the blanking intervals. For monochrome displays, this value should be set to 00h.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.4.6. AR13 Horizontal Pixel Panning Register I/O (and Memory Offset) Address: Default: Attributes: Read at 3C1h and Write at 3C0h; (index=13h) 0Uh (U=Undefined) Read/Write 7 4 3 0 Reserved (0000) Horizontal Pixel Shift Bit Description 7:4 Reserved. 3:0 Horizontal Pixel Shift 3-0. This field holds a 4-bit value that selects the number of pixels by which the image is shifted horizontally to the left.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.4.7. AR14 Color Select Register I/O (and Memory Offset) Address: Default: Attributes: 7 Read at 3C1h and Write at 3C0h; (index=14h) 0Uh (U=Undefined) Read/Write 4 Reserved (0000) Bit 9.5. 3 2 1 0 P7 P6 Alt P5 Alt P4 Description 7:4 Reserved. 3:2 Palette Bits P[7:6].
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R used to choose the color data position that is to be written to through the same data port. This arrangement allows the same data port to be used for reading from and writing to two different color data positions. Reading and writing the color data at a color data position involves three successive reads or writes since the color data stored at each color data position consists of three bytes.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.5.2. DACSTATE DAC State Register I/O (and Memory Offset) Address: Default: Attributes: 3C7h 00h Read Only 7 2 1 Reserved (000000) Bit 9.5.3. Description 7:2 Reserved. Read as 0s. 1:0 DAC State. This field indicates which of the two index registers was most recently written.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.5.5. DACDATA Palette Data Register I/O (and Memory Offset) Address: Default: Attributes: 3C9h Undefined Read/Write Bit 7:0 Description Palette Data. This byte-wide data port provides read or write access to the three bytes of data of each color data position selected using the Palette Read Index Register (DACRX) or the Palette Write Index Register (DACWX).
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.6.2. CR00 Horizontal Total Register I/O (and Memory Offset) Address: Default: Attributes: 3B5h/3D5h (index=00h) 00h Read/Write (Group 0 Protection) This register is used to specify the total length of each scan line. This encompasses both the part of the scan line that is within the active display area and the part that is outside of it. This register is extended to cover 16x12 resolution using CR35 and CR39. Bit 7:0 9.6.3.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.6.5. CR03 Horizontal Blanking End Register I/O (and Memory Offset) Address: Default: Attributes: 7 6 Reserved (0) 5 3B5h/3D5h (index=03h) 1UUU UUUUb (U=Undefined) Read/Write (Group 0 Protection) 4 Display Enable Skew Control 0 Horizontal Blanking End Bits 4:0 Bit Description 7 Reserved. Values written to this bit are ignored, and to maintain consistency with the VGA standard, a value of 1 is returned when this bit is read.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.6.7. CR05 Horizontal Sync End Register I/O (and Memory Offset) Address: Default: Attributes: 7 6 Hor Blank End Bit 5 5 3B5h/3D5h (index=05h) 00h Read/Write (Group 0 Protection) 4 Horizontal Sync Delay Bit 7 0 Horizontal Sync End Description Horizontal Blanking End Bit 5. This bit provides the most significant bit of a 6-bit value that specifies the end of the horizontal blanking period relative to its beginning.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.6.8. CR06 Vertical Total Register I/O (and Memory Offset) Address: Default: Attributes: 3B5h/3D5h (index=06h) 00h Read/Write (Group 0 Protection) Bit Description 7:0 Vertical Total Bits [7:0]. This field provides the 8 least significant bits of either a 10-bit or 12-bit value that specifies the total number of scan lines. This includes the scan lines both inside and outside of the active display area.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Bit 6 Description Vertical Display Enable End Bit 9. The vertical display enable end is a 10-bit or 12-bit value that specifies the number of the last scan line within the active display area. In standard VGA modes, where bit 0 of the I/O Control Register (CR80) is set to 0, the vertical display enable end is specified with a 10-bit value.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Bit 3 Description Vertical Blanking Start Bit 8. The vertical blanking start is a 10-bit or 12-bit value that specifies the beginning of the vertical blanking period relative to the beginning of the active display area. In standard VGA modes, where bit 0 of the I/O Control Register (CR80) is set to 0, the vertical blanking start is specified with a 10-bit value.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Bit Description 0 Vertical Total Bit 8. The vertical total is a 10-bit or 12-bit value that specifies the total number of scan lines. This includes the scan lines both inside and outside of the active display area. In standard VGA modes, where bit 0 of the I/O Control Register (CR80) is set to 0, the vertical total is specified with a 10-bit value.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.6.11. CR09 Maximum Scan Line Register I/O (and Memory Offset) Address: Default: Attributes: 7 6 5 Double Scanning Line Cmp Bit 9 Vert Blnk Start Bit 9 Bit 7 3B5h/3D5h (index=09h) 00h Read/Write 4 0 Starting Row Scan Count Description Double Scanning Enable. 0 = Disable. When disabled, the clock to the row scan counter is equal to the horizontal scan rate.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.6.12. CR0A Text Cursor Start Register I/O (and Memory Offset) Address: Default: Attributes: 3B5h/3D5h (index=0Ah) 00UU UUUUb (U=Undefined) Read/Write This cursor is the text cursor that is part of the VGA standard, and should not be confused with the hardware cursor and popup (a.k.a., cursor and cursor 2), which are intended to be used in graphics modes.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.6.14. CR0C Start Address High Register I/O (and Memory Offset) Address: Default: Attributes: 3B5h/3D5h (index=0Ch) Undefined Read/Write Bit Description 7:0 Start Address Bits [15:8] or [17:10].
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.6.15. CR0D Start Address Low Register I/O (and Memory Offset) Address: Default: Attributes: Bit 7:0 3B5h/3D5h (index=0Dh) Undefined Read/Write Description Start Address Bits [7:0] or [9:2]. This register provides either bits 7 through 0 of a 16 bit value that specifies the memory address offset from the beginning of the frame buffer, or bits 9 through 2 of a 32 bit buffer address at which the data to be shown in the active display area begins.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.6.17. CR0F Text Cursor Location Low Register I/O (and Memory Offset) Address: Default: Attributes: 3B5h/3D5h (index=0Fh) Undefined Read/Write This cursor is the text cursor that is part of the VGA standard, and should not be confused with the hardware cursor and popup (a.k.a., cursor and cursor 2), which are intended to be used in graphics modes.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.6.19. CR11 Vertical Sync End Register I/O (and Memory Offset) Address: Default: Attributes: 3B5h/3D5h (index=11h) 0U00 UUUUb (U=Undefined) Read/Write 7 6 5 4 Protect Regs 0:7 Reserved Vert Int Enable Vert Int Clear Bit 7 3 0 Vertical Sync End Description Protect Registers [0:7]. Note that the ability to write to Bit 4 of the Overflow Register (CR07) is not affected by this bit (i.e.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.6.20. CR12 Vertical Display Enable End Register I/O (and Memory Offset) Address: Default: Attributes: 3B5h/3D5h (index=12h) Undefined Read/Write Bit Description 7:0 Vertical Display Enable End Bits [7:0]. This register provides the 8 least significant bits of either a 10bit or 12-bit value that specifies the number of the last scan line within the active display area.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.6.22. CR14 Underline Location Register I/O (and Memory Offset) Address: Default: Attributes: 7 Reserved (0) 6 5 DWord Mode Count By 4 3B5h/3D5h (index=14h) 0UUU UUUUb (U=Undefined) Read/Write 4 0 Underline Location Bit Description 7 Reserved. Read as 0s. 6 DWord Mode.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.6.23. CR15 Vertical Blanking Start Register I/O (and Memory Offset) Address: Default: Attributes: 3B5h/3D5h (index=15h) Undefined Read/Write Bit Description 7:0 Vertical Blanking Start Bits [7:0]. This register provides the 8 least significant bits of either a 10-bit or 12-bit value that specifies the beginning of the vertical blanking period relative to the beginning of the active display area of the screen.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.6.25. CR17 CRT Mode Control I/O (and Memory Offset) Address: Default: Attributes: 3B5h/3D5h (index=17h) 0UU0 UUUUb (U=Undefined) Read/Write 7 6 5 4 3 2 1 0 CRT Ctrl Reset Word or Byte Mode Address Wrap Reserved (0) Count By 2 Horizontal Retrace Select Select Row Scan Cntr Compat Mode Support Bit 7 Description CRT Controller Reset. 0 = Forces horizontal and vertical sync signals to be inactive.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Bit Description 3 Count By 2. This bit is used in conjunction with bit 5 of the Underline Location Register (CR14) to select the number of character clocks are required to cause the memory address counter to be incremented. 0 = The memory address counter is incremented either every character clock or every 4 character clocks, depending upon the setting of bit 5 of the Underline Location Register.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Table 10.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Table 11.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.6.26. CR18 Line Compare Register I/O (and Memory Offset) Address: Default: Attributes: 3B5h/3D5h (index=18h) Undefined Read/Write Bit Description 7:0 Line Compare Bits [7:0]. This register provides the 8 least significant bits of a 10-bit value that specifies the scan line at which the memory address counter restarts at the value of 0.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.6.28. CR24 Test Register for Toggle State of Attribute Controller Register I/O (and Memory Offset) Address: Default: Attributes: 7 3B5h/3D5h (index=24h) 00h Read Only 6 0 Toggle Status Reserved (0000000) Bit 7 Description Toggle Status. Last write to attribute register was to: 0 = index port 1 = data port 6:0 9.6.29. Reserved. Read as 0s.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.6.30. CR31 Extended Vertical Display End Register I/O (and Memory Offset) Address: Default: Attributes: 7 3B5h/3D5h (index=31h) 00h Read/Write 4 3 Reserved (0000) Bit 0 Vertical Display End Bits 11:8 Description 7:4 Reserved. Read as 0s. This field must be 0s when this register is written. 3:0 Vertical Display End Bits [11:8].
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.6.31. CR32 Extended Vertical Sync Start Register I/O (and Memory Offset) Address: Default: Attributes: 7 3B5h/3D5h (index=32h) 00h Read/Write 4 3 Reserved (0000) Bit 0 Vertical Sync Start Bits 11:8 Description 7:4 Reserved. Read as 0s. This field must be 0s when this register is written. 3:0 Vertical Sync Start Bits [11:8].
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.6.32. CR33 Extended Vertical Blanking Start Register I/O (and Memory Offset) Address: Default: Attributes: 7 4 Reserved (0000) Bit 3B5h/3D5h (index=33h) 00h Read/Write 3 0 Vertical Blanking Start Bits 11:8 Description 7:4 Reserved. Read as 0s. This field must be 0s when this register is written. 3:0 Vertical Blanking Start Bits [11:8].
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.6.33. CR35 Extended Horizontal Total Time Register I/O (and Memory Offset) Address: Default: Attributes: 3B5h/3D5h (index=35h) 00h Read/Write 7 1 0 Reserved (0000000) Bit 7:1 0 9.6.34. Description Reserved. When this register is written to, these bits should be set to 0. Extended Horizontal Total (MSB that extends CR00).
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.6.35. CR40 Extended Start Address Register I/O (and Memory Offset) Address: Default: Attributes: 7 6 Start Addr Enable Reserved (0) 3B5h/3D5h (index=40h) 00h Read/Write 5 0 Start Address Bits 23:18 Bit Description 7 Extended Mode Start Address Enable. This bit is used only in extended modes, where bit 0 of the I/O Control Register (CR80) is set to 1, to signal the graphics controller to update the start address.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.6.36. CR41 Extended Offset Register I/O (and Memory Offset) Address: Default: Attributes: 7 3B5h/3D5h (index=41h) 00h Read/Write 4 3 Reserved (0000) Bit 0 Offset Bits 11:8 Description 7:4 Reserved. Read as 0’s. This field must be 0’s when this register is written. 3:0 Offset Bits [11:8] of a 12-bit value.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.6.38. CR70 Interlace Control Register I/O (and Memory Offset) Address: Default: Attributes: 7 3B5h/3D5h (index=70h) 00h Read/Write 6 0 Interlace Enable CRT Half-Line Value Bit Description 7 Interlace Enable. 0 = Selects non-interlaced CRT output (default). 1 = Selects interlaced CRT output. 6:0 9.6.39. CRT Half-Line Value.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 9.6.40. CR81 Reserved I/O (and Memory Offset) Address: Default: Attributes 3B5h/3D5h(index 81h) 00h Read/Write This register is not present in 2D. 7 0 Reserved (00000000) Bit Description 7:0 9.6.41. Reserved. (This register did something useful in ‘554, and was not completely removed from Portola database, even though it does nothing useful).
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 10. Programming Interface The Graphics Controller (GC) contains an extensive set of registers and instructions (also referred to as “Commands”) for controlling 2D, 3D, and video operations. This section describes the programmer’s interface to these registers and instructions. 10.1. Reserved Bits and Software Compatibility In many registers, instruction and memory layout descriptions, certain bits are marked as "Reserved".
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 10.3. GC Register Programming All of the GC registers (except for the PCI Configuration registers) are memory mapped. The base address of this 512 KB memory block is programmed in the MMADR PCI Configuration register. Note that 2D control registers (VGA and Extended VGA registers) are also located at their standard I/O locations. For more information on the registers, refer to the System Address Map chapter. 10.4.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 10.4.3. Instruction Parser The following figure shows a high-level diagram of the GC instruction interface.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 10.4.4. Ring Buffers (RB) The GC provides two Ring Buffer (RB) mechanisms through which instructions can be passed to the Instruction Parser. They are referred to as the Interrupt and Low-Priority RBs, and are basically identical, except for differences in arbitration rules and priority. Figure 27.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R • Head Wrap Count: This field is incremented by the IP every time the Head Offset wraps back to the start of the buffer. As it is included in the DWord written in the "report head" process, software can use this field to track IP progress as if the RB had a "virtual" length of 2048 times the size of the actual physical buffer. • Tail Offset: This is the QWord offset (from Start Address) where software will write the next instruction.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Software is required to use some mechanism to track instruction execution progress to determine the free space in the RB.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 10.4.6. Instruction Arbitration The Instruction Parser supports up to four sources of pending instructions: two Ring Buffers and two Batch Buffer sequences (one batch buffer per ring buffer). The IP employs a set of rules to arbitrate among these instruction stream sources. This section describes these rules and discusses the reasoning behind them. 10.4.6.1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R buffers, and the impact on latency and performance, should be carefully considered by software developers. 10.4.6.3. Instruction Arbitration Points The IP performs arbitration for instruction execution at the following points: • Continuously when idle (i.e.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 10.5. Instruction Format GC instructions are defined with various formats. The first DWord of all instructions is called the header DWord. The header contains the only field common to all instructions: the client field that determines the major GC unit that will process the instruction data.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 10.5.3. 3D Instructions The 3D instructions are used to program the 3D pipeline state and perform 3D, Stretch Blt, and MotionComp operations. All 3D state instructions are of fixed length, while the rendering instructions are all variable length. Refer to the Rendering Engine Instruction Chapter for a description of the 3D instructions. Figure 29. Instruction Format For First DWord Bits TYPE Parser 31:29 000 Rsvd.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Table 13.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Table 13.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 11. Instruction Parser Instructions 11.1. Introduction The Graphics Controller (GC) contains an extensive set of instruction for controlling 2D and 3D operations. This section describes the programmer’s interface to these instructions. The instructions can be categorized as follows: • 3D Instructions. The 3D pipeline states and processing functions are controlled by a set of 3D instructions.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 11.2.2. GFXCMDPARSER_BREAKPOINT_INTERRUPT This instruction will generate a breakpoint interrupt and cause the parser to stop until the interrupt is cleared by writing the Interrupt Identity Register. If the interrupting event is masked through the IMR, the parser continues parsing. However, if the event is unmasked in the IMR and the interrupt is not enabled through the IER, the parser halts until the IIR is cleared.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 11.2.4. GFXCMDPARSER_WAIT_FOR_EVENT This instruction can be used to pause instruction stream processing until a specific event occurs. Only one event can be specified -- specifying multiple events is UNDEFINED. The effect of the wait operation depends on the source of the instruction. If executed from a batch buffer, the instruction parser halts (and suspend instruction arbitration) until the event occurs.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 11.2.5. GFXCMDPARSER_FLUSH This instruction will flush all drawing engines and the frame buffer cache (a.k.a. local cache). In addition, it will conditionally invalidate the map cache. After this instruction is completed and followed by a store DWord, processor access to graphics memory will be coherent. 11.2.6. DWord Bit Description 0 31:29 Client: 000 – Instruction Parser 28:23 Opcode: 04h 22:2 Reserved: 000000h 1 Reserved.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 11.2.7. GFXCMDPARSER _DEST_BUFFER_INFO The GFXCMDPARSER DEST_BUFFER_INFO instruction is used to specify the information about the destination buffer. This is an "immediate" instruction and therefore software must ensure that the Rendering Engine and the local cache are flushed prior to modifying the destination buffer information.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 11.2.8. GFXCMDPARSER _FRONT_BUFFER_INFO The GFXCMDPARSER _FRONT_BUFFER_INFO instruction is used to initialize the base address of the scene to be display by the Display Engine (DE) (a.k.a. flip). There are two choices for this instruction. In the first choice, the Instruction Parser sends the base address to the DE where its update is synchronized to the display syncs (sync flip).
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 11.2.9. GFXCMDPARSER _Z_BUFFER_INFO This instruction is used to specify the base address and pitch of the Z buffer surface used by the 3D Rendering engine. This is an "immediate" command and therefore software must guarantee that the Rendering Engine and the local cache are flushed prior to modifying the z buffer information.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 11.2.11. GFXCMDPARSER_ARB_ON_OFF The GFXCMDPARSER_ARB_ON_OFF instruction is used to inform the input interface to turn on/off all the rings except the ring that this instruction is executed from. It can be use from a batch buffer. This instruction can be used to prevent other ring buffers from interrupting an instruction sequence. The format is: DWord Bits 0 31:29 Client: 000 – Instruction Parser 28:23 Opcode: 08h 22:1 Reserved.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 11.2.14. GFXCMDPARSER_LOAD_SCAN_LINES_EXCL This instruction is used to initialize the scan line window registers in the Display engine. If the display refresh is outside this window, the display engine asserts a signal that is used by the instruction parser to process the WAIT_FOR_EVENT instruction. This instruction overrides any previous INCL instruction.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 11.2.17. GFXCMDPARSER_BATCH_BUFFER The GFXCMDPARSER_BATCH_BUFFER instruction is used to inform the input interface to parse an instruction buffer. The address on the instruction buffers is in graphics memory that should translate to a physical address in main memory. Note that in case of an AGP device batch buffers can be in AGP memory only. The batch buffer instruction packet implements a protection ID.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 12. 2D Instructions This chapter contains the 2D graphics controller instructions. For each instruction the format specifies the functionality of a field. When an instruction does not require a field, it is ignored. All registers can only be written through instructions. No program I/O writing of the BLT registers is allowed. 12.1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 12.2.1. SETUP_BLT The setup instruction supplies common setup information including clipping coordinates used exclusively with the following 3 instructions: 1. 2. 3. PIXEL_BLT (PB) - 1 pixel write with the coordinate and solid pattern supplied for each pixel to be written. No non-solid patterns nor source operands are allowed. SCANLINE_BLT (SLB) - 1 scan line of color or mono pattern and destination are the only operands allowed.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R DWord 0 = BR00 0 1 = BR01 Bit 31:29 Description Client : 02h – 2D Processor 28:22 Instruction Target (Opcode) : 00h 21:05 Reserved. Must be Zero 04:00 Dword Length : 06h 31 Reserved. Must be Zero 30 Reserved. Must be Zero 29 Mono Source Transparency Mode: (1 = transparency enabled; 0 = use background) - TB only 28 Reserved. Must be Zero 27 Reserved. Must be Zero 26 Must Be One (‘1’).
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 12.2.2. SETUP_MONO_PATTERN_SL_BLT This setup instruction supplies common setup information including clipping coordinates used exclusively with the following instruction: • SCANLINE_BLT (SLB) - 1 scan line of monochrome pattern and destination are the only operands allowed. Clipping addresses and coordinates are inclusive. (The BLT Engine performs a trivial reject for this BLT before performing any accesses.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 12.2.3. PIXEL_BLT The Destination X coordinate and Destination Y Address is compared with the ClipRect registers. If it is within all 4 comparisons, then the pixel supplied in the SETUP_BLT instruction is written with the raster operation to (Destination Y Address + Destination X coordinate * bytes per pixel).
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 12.2.5. TEXT_BLT All monochrome source scan lines and pixels that fall within the ClipRect Y addresses and X coordinates are written (ignoring the raster operation) to (Destination Y Address + Destination X coordinate * bytes per pixel). Source expansion color registers are always in the SETUP_BLT. Note: All graphics controller BR03 fields (monochrome clipping parameters) are computed by the hardware while performing clipping.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 12.2.6. TEXT_Immediate_BLT This instruction allows the Driver to send data through the instruction stream, which eliminates the read latency of reading a source from memory. This allows graphics primitives such as Text to execute much faster. If an operand is in system cacheable memory and either is small or only accessed once, it can be copied directly to the instruction stream versus to graphics accessible memory.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 12.2.7. COLOR_BLT COLOR_BLT is the simplest BLT operation. It performs a color fill to the destination (with a possible ROP). The only operand is the destination operand, which is written dependent on the raster operation. The solid pattern color is stored in the pattern background register. • This instruction is optimized to run at the maximum memory write bandwidth. • Only a positive destination pitch is allowed.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 12.2.8. PAT_BLT PAT_BLT is used when there is no source and the color pattern is not trivial (is not a solid color only). The whole color pattern (8 x 8 pixels = 16, 32, or 64 DWs) is read at the beginning of the BLT and stored in the Texture Cache. The pattern vertical alignment specifies the first scan line of the pattern that is used. The horizontal alignment is relative to the destination from the lower bits of the destination address.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 12.2.9. MONO_PAT_BLT MONO_PAT_BLT is used when there is no source and the monochrome pattern is not trivial (is not a solid color only). The monochrome pattern is loaded from the instruction stream and the only memory accesses are for the destination operand, which is dependent on the raster operation. The pattern vertical alignment indicates on which byte to start.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 12.2.10. SRC_COPY_BLT This BLT instruction performs a color source copy where the only operands involved is a color source and destination of the same bit width. The source and destination operands may overlap, which means that the X and Y directions can be either forwards or backwards. The X direction field applies to both the destination and source operands. The source and destination pitches can be either sign.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 12.2.11. MONO_SRC_COPY_BLT This BLT instruction performs a monochrome source copy where the only operands involved is a monochrome source and destination. The source and destination operands cannot overlap, which means that the X direction must always be forward. All non-text monochrome sources are word aligned. At the end of a scan line the monochrome source, the bits until the next word boundary must be ignored.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R DWord Bit Description 4 31:16 Reserved. Must be Zero 4 = BR11 15:00 Number of Monochrome Source Quadwords - 1: (1 to 64k Quadwords = 64 to 4M bits) 5 = BR12 31:00 Source Address: (address of the first byte of the first pixel on the first scan line) (25:00 are implemented in Intel® 810 chipset) 6 31:24 Reserved. Must be Zero 6 = BR18 23:00 Source Background Color: 7 31:24 Reserved.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R DWord Bit 0 = BR00 31:29 Client : 02h – 2D Processor 28:22 Instruction Target (Opcode) : 61h 21:20 Reserved. Must be Zero 19:17 Monochrome source data bit position of the first pixel within a byte per scan line. 16 Description Reserved. Must be Zero 0 = BR11 15:00 Dword Length : 04+ DWL = (Number of Immediate double words)h 1 = BR13 31:30 Reserved.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 12.2.13. FULL_BLT The full BLT is the most comprehensive BLT instruction. It provides the ability to specify all 3 operands: destination, source, and pattern. The source and pattern operands are the same bit width as the destination operand. The whole color pattern (8 x 8 pixels = 8, 16, or 64 DWs) is read at the beginning of the BLT and stored in the Texture Cache. The pattern vertical alignment specifies which scan line of the pattern is used first.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R DWord Bit 3 = BR09 31:00 Description Destination Address: Address of the first byte to be written (25:00 are implemented in Intel® 810 chipset) 31:14 Reserved. Must be Zero 4 = BR11 13:00 Source Pitch (quadword aligned and signed): (13:00 are implemented in Intel® 810 chipset) 5 = BR12 31:00 Source Address: (25:00 are implemented in Intel® 810 chipset) 31:24 Reserved.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R DWord Bit 0 = BR00 31:29 Client : 02h – 2D Processor 28:22 Instruction Target (Opcode) : 46h 21:20 Reserved. Must be Zero 19:17 Monochrome source data bit position of the first pixel within a byte per scan line. 16:08 Reserved. Must be Zero 07:05 Pattern Vertical Alignment: (which scan line of the 8x8 pattern to start on) 04:00 Dword Length : 07h 31:30 Reserved.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 12.2.15. FULL_MONO_PATTERN_BLT The full BLT is the most comprehensive BLT instruction. It provides the ability to specify all 3 operands: destination, source, and pattern. The pattern operand is monochrome and the source operand is the same bit width as the destination operand. The monochrome pattern is loaded from the instruction stream. The pattern vertical alignment specifies which scan line of the pattern is used first.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R DWord Bit 2 = BR14 31:16 Destination Height (in scan lines): (28:16 are implemented in Intel® 810 chipset) 15:00 Destination Width (in bytes): (12:00 are implemented in Intel® 810 chipset) 31:00 Destination Address: Address of the first byte to be written 3 = BR09 Description (25:00 are implemented in Intel® 810 chipset) 4 = BR11 31:16 Reserved.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 12.2.16. FULL_MONO_PATTERN_MONO_SRC_BLT The full BLT provides the ability to specify all 3 operands: destination, source, and pattern. The pattern and source operands are monochrome. The monochrome pattern is loaded from the instruction stream. The pattern vertical alignment specifies which scan line of the pattern is used first. The destination address specifies the horizontal alignment.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R DWord Bit 1 = BR13 31 Solid Pattern Select: (1 = solid pattern; 0 = no solid pattern) 30 Reserved. Must be Zero 29 Mono Source Transparency Mode: (1 = transparency enabled; 0 = use background) 28 Mono Pattern Transparency Mode: (1 = transparency enabled; 0 = use background) 27 Reserved. Must be Zero 26 Must Be One (‘1’).
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 12.3. BLT Engine Instruction Definitions This section describes the BLT Engine instruction fields. These descriptions are in the format of register descriptions. For debug purposes, the read-only addresses indicated provide BLT Engine status. 12.3.1. BR00—BLT Opcode and Control Memory Offset Address: Default: Attributes: 40000h 0000 0000 RO; DWord accessible BR00 is the last executed instruction DWord 0.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Bit Descriptions 13 Text BLT. Current Opcode is Text BLT. 12 Scan Line BLT. Current Opcode is Scan Line BLT. 11 Pixel BLT. Current Opcode is Pixel BLT. 10:8 Destination Transparency Mode. These bits control whether or not the byte(s) at the destination corresponding to a given pixel will be conditionally written, and what those conditions are.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 12.3.2. BR01—Setup BLT Raster OP, Control, and Destination Offset Memory Offset Address: Default: Attributes: 40004h 0000 xxxx RO; DWord accessible BR01 contains the contents of the last Setup instruction DWord 1. It is identical to the BLT Raster OP, Control, and Destination Offset definition, but it is used with the following instructions: PIXEL_BLT, SCANLINE_BLT, and TEXT_BLT.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Bit Descriptions 28 Monochrome Pattern Transparency Mode. This bit applies only when the pattern data is monochrome. This bit determines whether or not the byte(s) at the destination corresponding to the pixel to which a given bit of the pattern data also corresponds will actually be written if that pattern data bit has the value of 1. This feature can make it possible to use the pattern as a transparency mask.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 12.3.3. BR02—Clip Rectangle Y1 Address Memory Offset Address: Default: Attributes: 40008h None RO; DWord accessible BR02 is loaded by either the SETUP_BLT or SETUP_MONO_PATTERN_SL_BLT instructions and is used with PIXEL_BLT, SCANLINE_BLT, or TEXT_BLT instructions. 31 26 25 Reserved. Must be Zero Clip Rectangle Y1 Address Bits [25:0] Bit 12.3.4. 0 Descriptions 31:26 Reserved. Must be Zero. The maximum GC graphics address is 64 MB.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 12.3.5. BR04—Clip Rectangle X1 and X2 Memory Offset Address: Default: Attributes: 40010h None RO; DWord accessible BR04 is loaded by either the SETUP_BLT or SETUP_MONO_PATTERN_SL_BLT instructions and is used with PIXEL_BLT, SCANLINE_BLT, or TEXT_BLT instructions. 31 28 27 Reserved. Must be Zero 15 12 16 Clip Rectangle X2 coordinate (right) [11:00] 11 Reserved.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 12.3.6. BR05—Setup Expansion Background Color Memory Offset Address: Default: Attributes: 31 24 40014h None RO; DWord accessible 23 Reserved. Must be Zero 0 Setup Expansion Background Color Bits [23:0] Bit Descriptions 31:24 Reserved. Must be Zero. 23:0 Setup Expansion Background Color Bits [23:0].
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 12.3.8. BR07—Setup Color Pattern Address Memory Offset Address: Default: Attributes: 31 4001Ch None RO; DWord accessible 26 25 Reserved. Must be Zero 15 16 Setup Color Pattern Address Bits [25:16] 6 5 Setup Color Pattern Address Bits [15:6] Bit 0 Reserved. Must be Zero Descriptions 31:26 Reserved. Must be Zero. The maximum GC graphics address is 64 MBs. 25:6 Pattern Address.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 12.3.9. BR08—Destination X1 and X2 Memory Offset Address: Default: Attributes: 40020h None RO; DWord accessible BR08 is loaded by either PIXEL_BLT, SCANLINE_BLT, or TEXT_BLT instructions. The PIXEL_BLT instruction only writes the destination X coordinate register. 31 28 27 Reserved. Must be Zero 15 12 16 Destination X2 coordinate (right) [11:00] 11 Reserved.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 12.3.10. BR09—Destination Address and Destination Y1 Address Memory Offset Address: Default: Attributes: 31 26 40024h None RO; DWord accessible 25 Reserved. Must be Zero 0 Destination and Destination Y1 and Y Address Bits [25:0] Bit Descriptions 31:26 Reserved. Must be Zero. 25:0 Destination and Destination Y1 and Y Address Bits. These 26 bits specify the starting pixel address of the destination data.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 12.3.12. BR11—BLT Source Pitch (Offset) or Monochrome Source Quadwords Memory Offset Address: Default: Attributes: 4002Ch None RO; DWord accessible 31 14 Reserved Bit 13 0 Source Pitch (Offset) or Monochrome Source Quadwords Descriptions 31:14 Reserved. 13:0 Source Pitch (Offset) or Monochrome Source Quadwords.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 12.3.13. BR12—Source Address Memory Offset Address: Default: Attributes: 31 26 Reserved. Must be Zero Bit 40030h None RO; DWord accessible 25 0 Source Address Bits [25:0] Descriptions 31:26 Reserved. Must be Zero. The maximum GC Graphics address is 64 MBs. 25:0 Source Address Bits [25:0].
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 12.3.14. BR13—BLT Raster OP, Control, and Destination Pitch Memory Offset Address: Default: Attributes: 40034h 0000 xxxx RO; DWord accessible 31 30 29 28 27 26 Sol Pat Sel X Dir Mon Src Trans Mon Pat Trans Src Sel Mode Dyn Col En 15 14 24 23 Dynamic Color Depth 16 Raster Operation Select 13 0 Reserved. Must be Zero Destination Pitch (Offset) Bit Descriptions 31 Solid Pattern Select.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Bit Descriptions 28 Monochrome Pattern Transparency Mode. This bit applies only when the pattern data is monochrome. This bit determines whether or not the byte(s) at the destination corresponding to the pixel to which a given bit of the pattern data also corresponds will actually be written if that pattern data bit has the value of 1. This feature can make it possible to use the pattern as a transparency mask.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 12.3.15. BR14—Destination Width & Height Memory Offset Address: Default: Attributes: 40038h None RO; DWord accessible BR14 contains the values for the height and width of the data to be BLT. If these values are not correct, such that the BLT Engine is either expecting data it does not receive or receives data it did not expect, the system can hang. 31 29 28 Reserved. Must be Zero 15 13 Destination Height 12 Reserved.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 12.3.16. BR15—Color Pattern Address Memory Offset Address: Default: Attributes: 31 4003Ch None RO; DWord accessible 26 25 Reserved. Must be Zero 15 16 Color Pattern Address Bits [25:16] 6 5 Color Pattern Address Bits [15:6] Bit 0 Reserved. Must be Zero Descriptions 31:26 Reserved. Must be Zero. The maximum GC graphics address is 64 MBs. 25:6 Color Pattern Address. These 20 bits specify the starting address of the pattern.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 12.3.17. BR16—Pattern Expansion Background & Solid Pattern Color Memory Offset Address: Default: Attributes: 31 24 40040h None RO; DWord accessible 23 Reserved. MBZ 0 Pattern Expansion Background Color Bits [23:0] Bit Descriptions 31:24 Reserved. Must be Zero. 23:0 Pattern Expansion Background Color Bits [23:0].
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 12.3.19. BR18—Source Expansion Background, and Destination Color Memory Offset Address: Default: Attributes: 31 24 40048h None RO; DWord accessible 23 Reserved. Must be Zero 0 Source Expansion Background Color Bits [23:0] Bit Descriptions 31:24 Reserved. Must be Zero. Debug implementation specific [31:25] = bmnewcliplw[6:0]. 23:0 Source Expansion Background Color Bits [23:0].
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 12.3.21. S_SLADD—Source Scan Line Address Memory Offset Address: Default: Attributes: 31 26 40074h None RO; DWord accessible 25 Reserved. Must be Zero Bit 0 Source Scan Line Address Bits [25:0] Descriptions 31:26 Reserved. Must be Zero. The maximum GC graphics address is 64 MBs. 25:0 Source Scan Line Address. These 26 bits are used by the over scan line fetching state machine to address the source data.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 12.3.23. D_SLRADD—Destination Scan Line Read Address Memory Offset Address: Default: Attributes: 31 26 Reserved. Must be Zero Bit 4007Ch None RO; DWord accessible 25 0 Destination Scan Line Read Address Bits [25:0] Descriptions 31:26 Reserved. Must be Zero. The maximum GC Graphics address is 64 MBs. 25:0 Destination Address. These 26 bits specify the scan line address of the destination data being read. This is a working register.
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Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 13. Rendering Engine Instructions This chapter describes the 3D instructions and motion compensation instruction that controls the Graphics controller (GC) rendering engine. The GC Rendering Engine shall receive all software driver instructions through the instruction interface (ring buffers). 13.1. GFXPRIMITIVE This instruction performs most of the rendering operations performed by the GC.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 13.1.3. Position Mask In Variable vertex format, a position mask is sent to indicate the present of X, Y, Z, and 1/W parameters. If 1/W (RHW) is declared not present in the vertex packet, hardware forces 1/w equal to 1. In the case Z is declared not present, the Z value of the last triangle from the last vertex instruction packet will be used for the triangles in this packet. 13.1.4.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 13.1.6. Variable Length Vertex Formats for Rendering Instructions The GC supports variable length vertex formats. These formats are determined, by enable bits contained in the variable length vertex format (VLVF) instructions. The following table specifies the attributes associated with each vertex. The order of the attributes must be strictly observed.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 13.1.7. GFXVERTEX Rendering Processor instructions include data per vertex. The vertex data format is the same for these instructions. GFXVERTEX is not an instruction, but a definition of this vertex data format. GFXVERTEX does not include an instruction header since it is not an instruction. The GFXVERTEX format is: Dword Bits 0 31:4 X position : Relative to origin drawing rectangle or dest buffer. Valid data range is -383 to 1663.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 13.2. GFXRENDERSTATE_VERTEX_FORMAT Flexible Vertex Format Packet DWord Bit Description 0 31:29 Client : 03h – Render Processor 28:24 3DState24 : 05h 23:12 Reserved : 00h 11:8 Texture Coordinate Count: This field identifies how many coordinates are present in the vertex. The valid range is 0–2.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 13.3. GFXBLOCK The GFXBLOCK instruction is used with Motion Compensation. It is a variable length instruction, which contains intra-coded/correction data at the end of the instruction. The DWORD_LENGTH must correspond to the Block Pattern Bits that identify which quadrants of the block have associated correction data. When the horizontal or vertical block pattern are disabled the block pattern bits are assumed to be set.
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Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R DWord Bits 2 31:26 Reserved: 00h 25:16 Horizontal Origin: An unsigned integer specifying both the upper-left pixel of the destination block and the origin of the motion vectors in the reference frame(s). This value must be a multiple of the width. The valid range is 0 – 1023.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 13.3.1. Motion Vector Format The motion vectors provided in the GFXBLOCK instruction have the following format. DWord Bits 0 31:16 15:0 13.4. Description Horizontal Motion Vector Value: The value is signed 2’s complement fixed point with the following formats, depending on the Motion Vector Precision bits. The range defines the clamp boundaries for the values. Precision Format Range 1 /2 pixel S14.1 [-1024.0–1023.5] 1 /4 pixel S13.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 13.5. GFXRENDERSTATE_MAP_TEXELS The Mapping Engine is capable of generating at most two texels per pixel. The texels may be obtained from two separate maps or the same map using different u,v coordinates. The binding between the texels which are generated by the engine and the coordinate set and the map information state is specified with this instruction. The texels are generated in the order specified by the Texel Index.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 13.6. GFXRENDERSTATE_MAP_COORD_SETS The Mapping Engine is capable of generating at most two map coordinate sets (u and v addresses) per pixel. Each output texel may be related to separate coordinate sets or to the same coordinate set, as shown below. The vertices of a GFXPRIMITIVE instruction may have 0, 1 or 2 map coordinate sets assigned with varying settings associated with each coordinate set.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R DWord Bit Description 0 31:29 Client : 03h – Rendering Engine 28:24 3DState16 : 1Ch 23:19 Opcode : 1h 18:17 Reserved: 00h (Additional Coordinate Sets) 16 Update Coordinate Set Index : The valid range is 0–1. 15 Normalized Coordinate Set Mask : 0 = Do not update; 1 = Update 14 Normalized Coordinate Set : 0 = Coordinates are not normalized. 1 = Coordinates are normalized.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 13.7. GFXRENDERSTATE_MAP_INFO The Mapping Engine is capable of fetching texels from at most two maps per pixel. This instruction specifies the attributes relating to the location and format of the map. Two different texels can be fetched from the same map. Figure 33. State Variable Relationships Coordinate Sets Map Information Texels Blending Stages Table 14 identifies four classes of surface formats for the supported maps in the GC.
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Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R DWord Bit 0 31:29 Client : 03h – Rendering Engine 28:24 3DstateMW : 1Dh 23:16 Opcode : 0h 15:0 DWORD_LENGTH : 2h 31:29 Reserved: 00h 1 Description 28 Update Map Index : The valid range is 0–1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R DWord Bit 1 18 Description Color Space Conversion Enable: 0 = Do not perform conversion. 1 = Perform color space conversion assuming biased chromanance values. 17 Vertical Line Stride: The number of lines to skip between logically adjacent lines. The Forward/Backward Reference Picture Structure bits override this value when processing the GFXBLOCK instruction. 0 = Do not skip any lines. 1 = Skip 1 line.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R DWord Bit Description 2 31 Dimensions are Powers of 2: This field specifies whether the following Height and Width fields of the map are specified as the log2 of the actual dimension or as the actual height or width. If the actual values are used, the coordinate set addresses must be non-normalized and are clamped (they can not be wrapped or mirrored).
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 13.8. GFXRENDERSTATE_MAP_FILTER The Mapping Engine is capable of fetching texels/pixels from at most two maps per pixel. This instruction specifies the filter settings associated with specified map. Figure 35. State Variable Relationships Coordinate Sets Map Information Texels Blending Stages Anisotropic filtering produces superior image quality with reduced performance. Adjusting the LOD bias can contain the aspect ratio of the filter.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R DWord Bit 0 31:29 Client : 03h – Rendering Engine 28:24 3DState16 : 1Ch 23:19 Opcode : 2h 18:17 Reserved: 00h (Additional Maps) 16 15:13 Description Update Map Index : The valid range is 0–1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 13.9. GFXRENDERSTATE_MAP_LOD_LIMITS The limits of the Level of Detail calculation can be controlled within GC for each Map. These values are specified in the following instruction as follows. Figure 36.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 13.10. GFXRENDERSTATE_MAP_LOD_CONTROL The Level-of-Detail dither weight and bias can be associated with each map using the following instruction. Figure 37. State Variable Relationships Coordinate Sets Map Information Texels Blending Stages Dword Bit 0 31:29 Client : 03h – Rendering Engine 28:24 3DState16 : 1Ch 23:19 Opcode : 4h 18:17 Reserved: 00h (Additional Maps) 16 15:11 Description Update Map Index : The valid range is 0–1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 13.11. GFXRENDERSTATE_MAP_PALETTE_LOAD The Texture Palette is loaded using the following instruction. All 256 entries of the texture palette must be loaded every time this command packet is sent. In other words, even if only one entry of the texture palette needs to be updated, all 256 entries must be loaded and sent using this command packet. Figure 38.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 13.12. GFXRENDERSTATE_MAP_COLOR_BLEND_STAGES The Rendering Engine supports three map color blend stages for the red, green, and blue channels. Any of these stages may perform an operation utilizing up to two texels from the Mapping Engine, the iterated face color, the iterated alpha and/or a constant color. Figure 39.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Dword Bit Description 0 31:29 Client : 03h – Rendering Engine 28:24 3DState24 : 00h 23:22 Reserved: 00h (Additional Blending Stages) 21:20 Update Blending Stage Index : The valid range is 0–2.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Dword Bit 0 6 Description Invert Color Arg2: 0 = Do not Invert Argument 1 = Invert Argument 5 4:0 Color Operation Mask : 0 = Do not update; 1 = Update Color Operation: Valid values are : 00h = The user must explicitly disable each blend stage that is not used. Note: The user must ensure that if a blend stage is disabled, all higher number blend stages must be disabled too. E.g. It is invalid to disable stage 2 and use only stages 1 and 3.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 13.13. GFXRENDERSTATE_MAP_ALPHA_BLEND_STAGES The Rendering Engine supports three map color blend stages for the alpha channel. Any of these stages may perform an operation utilizing the alpha channel from up to two texels from the Mapping Engine, the iterated alpha and/or a constant color. Figure 40. State Variable Relationships Coordinate Sets Map Information Texels Blending Stages The following equations are supported by each blending stage.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R The settings for these stages are specified in the following instruction. DWord Bit Description 0 31:29 Client : 03h – Rendering Engine 28:24 3DState24 : 01h 23:22 Reserved: 00h (Additional Blending Stages) 21:20 Update Blending Stage Index : The valid range is 0–2.
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Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 13.15. GFXRENDERSTATE_COLOR_CHROMA_KEY ColorKey and ChromaKey are terms used to describe two methods of removing a specific color or range of colors from a map that is applied to a primitive.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R The Intel® 810 chipset implementation of Blend color/chroma key mode is, again, different than what Microsoft eventually defined for DX7*. DX7* specifies that any contributing texels which match the key must be replaced by black with zero alpha prior to application of the normal texture filter.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 13.16. GFXRENDERSTATE_SRC_DST_BLEND_MONO The state variable Specular_RGB_Enable is set in the graphics command GFXRENDERSTATE_SRC_DST_BLEND_MONO. It is also dependent on the value of the state variable Specular_Enable, which is set in the graphics command GFXRENDERSTATE_BOOLEAN_ENA_1. Table 15.
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Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Bit Description 31:29 Client : 03h – Rendering Processor 28:24 3DState24 : 08h 23:16 Reserved : 00h 15 Specular RGB State Mask : 0 = Do Not Update 1 = Update 14 Specular RGB Enable : 0 = Disable (default) 1 = Enable Controls specular color interpolation. When enabled, a full RGB specular color is interpolated, otherwise a monochrome specular value is interpolated.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 13.17. GFXRENDERSTATE_Z_BIAS_ALPHA_FUNC_REF DWord Bit Description 0 31:29 Client : 03h – Render Processor 28:24 3DState24NP (Non-pipelined) : 14h 23 Reserved : 0 22 Z Bias State Mask : 1 = Update ; 0 = Do Not Update 21:14 13 12:9 Z Bias : This is a signed value that is added to the source Z value prior to the Z compare function.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 13.18. GFXRENDERSTATE_LINE_WIDTH_CULL_SHADE_ MODE The provoking vertex refers to the vertex that selected the flat shaded color for the primitive. In the OpenGL* specification, the third/second (triangle/line) vertex should used. In D3D* specification, the first vertex should be used. There is an additional mode to allow the selection of the common vertex for triangle fan primitive and the third/second (triangle/line) vertex for other primitives.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 13.19. GFXRENDERSTATE_BOOLEAN_ENA_1 Dword Bit Description 0 31:29 Client : 03h – Render Processor 28:24 3DState24 : 03h 23:20 Reserved : 0h 19 Specular Setup Enable Mask : 1 = Update; 0 = Do Not Update 18 Specular Setup Enable : 0 = Disable (default), 1 = Enable This SV enables specular gradient calculations in the Setup Unit (independent of other specular SVs). This bit is currently not used.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 13.20. GFXRENDERSTATE_BOOLEAN_ENA_2 DWord Bit Description 0 31:29 Client : 03h – Render Processor 28:24 3DState24 : 04h 23:18 Reserved : 00h 17 Mapping Cache Enable Mask : 1 = Update; 0 = Do Not Update 16 Mapping Cache Enable : 1 = Enable, 0 = Disable (default) Any change made to the Mapping Cache Enable state variable must be followed by a GFXCMDPARSER_FLUSH instruction to cause the hardware to flush the 3D pipeline.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 13.21. GFXRENDERSTATE_FOG_COLOR The GFXRENDERSTATE_FOG_COLOR state instruction format is: 13.22. DWord Bit Description 0 31:29 Client : 03h – Render Processor 28:24 3DState24NP (Non-pipelined) : 15h 23:19 Fog Color Red : Bits 7:3 of the red fog color component. The default value is 0. (unsigned int) 18:16 Reserved : 0h 15:10 Fog Color Green : Bits 7:2 of the green fog color component. The default value is 0.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R DWord Bits 0 31:29 Client : 03h – Rendering Engine 28:24 3DStateMWNP (Non-pipelined) : 1Dh 23:16 Opcode : 80h 15:0 DWORD_LENGTH : 3 1 31 Description Drawing/Scissor Rectangle clipping Enable (for validation purpose only). This bit should be set to enable in normal mode.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 13.23. GFXRENDERSTATE_SCISSOR_ENABLE Only inclusive mode scissoring is supported.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 13.24. GFXRENDERSTATE_SCISSOR_RECTANGLE_INFO The coordinate in this instruction packet is relative to the origin (upper left corner, DWord #4) of the drawing rectangle defined in the GFXRENDERSTATE_DRAWING_RECTANGLE_INFO packet. The coordinates of the scissor rectangle do not need to be clipped to screen boundary before sent to hardware.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 13.25. Stipple Pattern The stipple pattern is a 4x4 bit memory that serves as pixel write mask. When stipple is enabled, the frame buffer will only be updated with pixels that have 1’s in their associated stipple pattern memory locations. The stipple pattern memory maps to a 4x4 pixel grid. The stipple pattern repeats for x and y coordinates on every span (4x4 pixels). The purpose of the stipple pattern is mostly for testing.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 13.26. GFXRENDERSTATE_ANTI_ALIASING The Anti-aliasing packet defines the anti-aliasing enable, bounding-box expansion, line anti-aliasing region, polygon anti-aliasing region, and edge flag enable State variables. The anti-aliasing enable state variable turns on anti-aliasing of polygons and lines. The Bounding Box enclosing the triangle or line is expanded in all directions by the bounding box expansion value (in pixels) .
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 13.27. GFXRENDERSTATE_PROVOKING_VTX_PIXELIZATION _RULE The provoking vertex state variables provide the flexibility of selecting the flat-shaded vertex for the first triangle/line of a primitive packet. The subsequent flat-shaded vertices are in incrementing order, except in the case of triangle fans with common flat shaded vertex. Separate State variables are provided for triangles and lines.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R DWord Bits 0 31:29 Client : 03h – Rendering Engine 28:24 3DState24 : 07h 23:13 Reserved: 0000h 12 Description Small Triangle Filter Enable Mask : 1 = Update ; 0 = Do Not Update 11 Small Triangle Filter Enable: If Set then Small Triangles i.e triangles which donot cover any pixels, and are either vertical or horizontal will be filtered out.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 13.28. GFXRENDERSTATE_DEST_BUFFER_VARIABLES The GFXRENDERSTATE_DEST_BUFFER_VARIABLES instruction is used to specify the information about the destination buffer. This information is used to initialize rendering hardware parameters. The destination buffer contains the pixel color data for the scene being rasterized by the 3D Rendering Engine. This is a non-pipelined state variable. Two examples of how the Origin BIAS works are shown below.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R DWord Bit Description 1 31:24 Reserved: 00h 23:20 Destination Origin Horizontal Bias: This is an unsigned value (0.4) that is used to bias the origin of the X values associated with the vertices of a primitive. The unbiased origin is located in the upper-left corner of a square pixel with the center located at 0.5, 0.5. A bias value of ½ (8h) would move the origin toward the right, such that an X value of 0.0 would specify the center of a pixel.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 13.29. Programming Hints/Rules The following provides programming hints/rules for 3D, Motion Compensation, and Stretch Blitter operations. Drawing and Scissor Rectangles • Must declare a Drawing Rectangle packet first before Scissor Rectangle packet • Coordinates of Drawing Rectangle must be Xmax > Xmin and Ymax > Ymin • Drawing Rectangle width and height must be greater than 1pixel for Rectangle primitives.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 3D instruction GFXRENDERSTATE_BOOLEAN_EN_2. To ensure proper hardware operation, software must follow up with the GFXCMDPARSER_FLUSH instruction to cause the hardware to flush the 3D pipeline. Color Calculator • Texture blend stage 0 must always be enabled. For untextured primitives, a select arg operation should be programmed. This is equivalent to a pass through operation to the next pipeline stage.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R • Z buffering is not supported (Z_en is overloaded to 0). • State variables that have a context1 are: blend_en, dest_blend(3:0), src_blend(3:0), xoffset(11:0), yoffset(11:0), all Dest Buffer format variable packet, all Map Info packet, Map Cache enable. • Limit support on FVF packet format is supported: TX coordinate count =1, Specular_Fog_Present=0, Diffuse_Alpha_Present= programmable, Z_Offset_Present=0, Position Mask= programmable.
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Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 14. Clock Control Registers The clock control registers are accessed by writing to the memory mapped address offset. The Intel® 815 chipset has three PLLs to generate all the clocks. The Host PLL generates the host clock whose frequency is controlled by an external strap. In addition, the Host PLL generates the system and local memory core clock and graphics core clock. The Hub PLL generates the clock for the Hub Interface unit.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Example Programming Sequence (DCLK2) 1. Write the Display Clock 2 Divisor register with the M-REG value and N-REG value. 2. Write the clock 2 byte of the Display & LCD Clock Divisor Select Register with the P-REG value. 3. Write the MSR register, bit 3 = '1', to select DCLK2. Example Programming Sequence (LCD CLK) 1. Write the LCD clock Divisor register with the M-REG value and N-REG value. 2.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 14.3. DCLK_1D—Display Clock 1 Divisor Register Address Offset: Default Value: Attribute: Size: 06004h–06007h 00100053h R/W 32 bits The Display Clock 1 Divisor register and the Display & LCD Clock Divisor Select Register are programmed with the loop parameters to be loaded into the clock synthesizer. Data is written to the Display Clock 1 Divisor register followed by a write to the Clock 1 byte of the Display & LCD Clock Divisor Select Register.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 14.4. DCLK_2D—Display Clock 2 Divisor Register Address Offset: Default Value: Attribute: Size: 06008h–0600Bh 00030013h R/W 32 bits The Display Clock 2 Divisor register and Display & LCD Clock Divisor Select Register are programmed with the loop parameters to be loaded into the clock synthesizer. Data is written to Display Clock 2 Divisor register followed by a write to the Clock 2 byte of the Display & LCD Clock Divisor Select Register.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 14.5. LCD_CLKD—LCD Clock Divisor Register Address Offset: Default Value: Attribute: Size: 0600Ch–0600Fh 00030013h R/W 32 bits The LCD Clock Divisor register and Display & LCD Clock Divisor Select Register are programmed with the loop parameters to be loaded into the clock synthesizer. Data is written to LCD Clock Divisor register followed by a write to the LCD Clock byte of the Display & LCD Clock Divisor Select Register.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 14.6. DCLK_0DS—Display & LCD Clock Divisor Select Register Address Offset: Default Value: Attributes: Size: 06010h–06013h 40404040h R/W 32 bits Display clock i {i=0 to 2} becomes effective after programming the appropriate byte i {i = 0 to 2}in this register. LCD clock becomes effective after programming byte 3 in this register.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Bit 22:20 Description Post Divisor Select clock 2. 000 = Divide by 1 001 = Divide by 2 010 = Divide by 4 011 = Divide by 8 100 = Divide by 16 (default) 101 = Divide by 32 11x = Reserved 19 Reserved. 18 VCO Loop Divide clock 2. 0 = Divided by 4*M (default) 1 = Divided by 16*M 17:15 Reserved. 14:12 Post Divisor Select clock 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 14.7. PWR_CLKC—Power Management and Miscellaneous Clock Control Address Offset: Default Value: Attribute: Size: 6014h–06017h 0000 0101 h R/W 32 bits 31 17 16 Reserved 15 12 11 10 9 8 1 0 Display Clock PLL VCO Internal DAC Enable Reserved 7 2 Reserved Bit 31:2 1 Description Reserved. Display Clock PLL VCO 0 = Enable (default) 1 = Disable 0 Internal DAC Enable. 0 = Disables the internal DAC (PowerDown).
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 15. Overlay Registers This chapter contains the Overlay and Gamma Correction registers and an Overlay instruction. The current graphics controller implements one overlay that is referred to as Overlay 0. Note that the Overlay 0 control registers are indirectly written by first setting up a buffer in memory and then instructing the graphics controller to update the on-chip registers from this buffer.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Table 16. Overlay Register/Instruction Categories Register/Instruction Category Overlay 0 Register Update Address (OV0ADD) Mem. Address Offset 30000h Comment • Used to update Overlay 0 registers. • Provides physical memory address of buffer area used for updating on-chip registers • Write of OV0ADD register causes hardware to update on-chip registers on next VBLANK.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 15.1. OV0ADD—Overlay 0 Register Update Address Register Memory Address Offset: Default Value: Access: Size: 30000h–30003h 00000000 R/W 32 bits This register provides a physical memory address that will be used on the next register update for Overlay 0. This register is double buffered to allow it to be updated during overlay display.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 15.2. DOV0STA—Display/Overlay 0 Status Register Memory Address Offset: Default Value: Access: Size: 30008h–3000Bh 0000 5000h RO 32 bits This read-only register indicates the status for the overlay. References to display are either the primary timing generator or the secondary timing generator depending on which is currently being used. 31 30 24 Reg Update Status Reserved 23 21 Reserved 20 19 15 Overlay 0 Current Buffer/Field.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Bit 20:19 Description Overlay 0 Current Buffer/Field. This field indicates the Current Buffer. Updated at display VBLANK before the interrupt, this field is only valid when in field (interlaced) mode. 00 = Buffer 0 Field 0 01 = Buffer 0 Field 1 10 = Buffer 1 Field 0 11 = Buffer 1 Field 1 18:15 14 Reserved. Not Active Pixel. This bit indicates the Display Horizontal Blank Active state (includes Border).
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R These registers determine the characteristics of the gamma correction for the overlay data. Each register is 32 bits wide. The registers are written to and read from together when accessed from the PCI. The GAMCxx registers are not double buffered and should only be updated when the Overlay Engine is disabled. During operation, the bytes of these registers are read independently. These registers are dependent on the R, G, or B pixel values.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 15.3.1.2. Mathematical Gamma Correction For Overlay Gamma correction is a function that corrects for non-linearity between display phosphor brightness as a function of electron beam current.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R As shown, the inputs to the function are: • PCI Register Bus: The chip internal PCI data bus and the appropriate register decodes for loading the Gamma breakpoint values • Red In 2e07:00: The Red color component of the Overlay Stream • Green In 2e07:00: The Red color component of the Overlay Stream • Blue In 2e07:00: The Red color component of the Overlay Stream The output of the function is: • Red Out: The Gamma corrected Red color component.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R The following gives a more detailed description of the algorithm.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 15.4. Memory Offset Registers 15.4.1. Overlay Buffer Pointer Registers These registers provide address pointers into the system memory or Local memory buffer areas. The buffers must be QWord aligned. Pixel panning on a pixel basis is done using the byte addresses. Overlay buffers need to be QWord aligned and the stride should be a QWord multiple. Buffer pointers should always be aligned to the natural boundaries based on the data format.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 15.4.1.2. OBUF_1Y—Overlay Buffer 1 Y Pointer Register Memory Address Offset: On-chip Reg. Mem Addr Offset: Default Value: Access: Size: 31 26 25 Reserved 0 Overlay Buffer 1 Y Pointer Bit 15.4.1.3. 04h (R/W) 30104h (RO; debug path) 00h see address offset above 32 bits Description 31:26 Reserved. 25:0 Overlay Buffer 1 Y Pointer. For Y Planar or packed color data (byte address).
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 15.4.1.4. OBUF_0V—Overlay Buffer 0 V Pointer Register Memory Address Offset: On-chip Reg. Mem Addr Offset: Default Value: Access: Size: 31 26 25 Reserved Description 31:26 Reserved. 25:0 Overlay Buffer 0 V Pointer. This register is used for YUV Planar Modes only. It points to the start of the V addresses in the interleaved UV formats (byte address). OBUF_1U—Overlay Buffer 1 U Pointer Register Memory Address Offset: On-chip Reg.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 15.4.1.6. OBUF_1V—Overlay Buffer 1 V Pointer Register Memory Address Offset: On-chip Reg. Mem Addr Offset: Default Value: Access: Size: 31 26 14h (R/W) 30114h (RO; debug path) 00h see address offset above 32 bits 25 0 Reserved Overlay Buffer 1 V Pointer Bit 15.4.2. Description 31:26 Reserved. 25:0 Overlay Buffer 1 V Pointer. This register is used for YUV Planar Modes only.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 15.4.3. Overlay Initial Phase Registers Provides a spatial sub-pixel accurate adjustment. This value is always a fractional positive number that when combined with the subtract one from initial phase bit, the possible range for initial phase becomes 1
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 15.4.3.2. UV_VPH—UV Vertical Phase Register Memory Address Offset: On-chip Reg. Mem Addr Offset: Default Value: Access: Size: 31 20 20h (R/W) 30120h (RO; debug path) 00h see address offset above 32 bits 19 UV Vertical Phase 1 16 4 3 UV Vertical Phase 0 Bit 15.4.3.3. 15 Reserved 0 Reserved Description 31:20 UV Vertical Phase 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 15.4.3.4. INIT_PH—Initial Phase Register Memory Address Offset: On-chip Reg. Mem Addr Offset: Default Value: Access: Size: 28h (R/W) 30128h (RO; debug path) 00h see address offset above 32 bits 31 6 Reserved Bit 280 5 0 Initial Phase minus one Description 31:6 Reserved. 5:0 Initial Phase minus one. These bits provide a method of creating a negative initial phase.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 15.4.4. Overlay Destination Window Position/Size Registers These registers allow for the positioning of the overlay data relative to the graphics display or the secondary display active region. It allows pixel accurate positioning. When using a secondary display, the area outside the overlay windows will be black RGB(0,0,0). 15.4.4.1. DWINPOS—Destination Window Position Register Memory Address Offset: On-chip Reg.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 15.4.5. Overlay Source Size Registers These registers provide information to the overlay engine on what data needs to be fetched from memory. If the overlay destination window is smaller than the result of the scaled up source, it will be clipped on the right and bottom of the overlay window. The source data is clipped within one QWord. Source width must not specify an additional QWord or more of data that is not required to satisfy the destination.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 15.4.5.2. SWIDQW—Source Width In QWords Register Memory Address Offset: On-chip Reg. Mem Addr Offset: Default Value: Access: Size: 31 24 Reserved Bit 23 38h (R/W) 30138h (RO; debug path) 00h see address offset above 32 bits 16 UV Source Width in QWs 15 9 Reserved 8 0 Y/RGB Source Width in QWs Description 31:24 Reserved. 23:16 UV Source Width in QWords. The number of QWs contained in a single line of planar UV source data.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 15.4.5.3. SHEIGHT—Source Height Register Memory Address Offset: On-chip Reg. Mem Addr Offset: Default Value: Access: Size: 31 26 Reserved Bit 3Ch (R/W) 3013Ch (RO; debug path) 00h see address offset above 32 bits 25 16 UV Source Height 15 11 Reserved 10 0 Y/RGB Source Height Description 31:26 Reserved. 25:16 UV Source Height. In packed formats this is unused.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 15.4.6. Overlay Scale Factor Registers These registers provide the scaling information that is used to specify the amount of vertical and horizontal scaling. In the case of YUV formats, there are independent scale factors for Y and UV data to compensate for the various formats that include sub-sampled UV data. Up or down scaling is set using the bits of the command word.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 15.4.6.2. UVSCALE—UV Scale Factor Register Memory Address Offset: On-chip Reg. Mem Addr Offset: Default Value: Access: Size: 44h (R/W) 30144h (RO; debug path) 00h see address offset above 32 bits 31 20 19 Vertical Scale Factor UV 15 14 Reserved Reserved 3 Horizontal Scale Factor UV 2 Reserved 1 0 UV Down Scale Integer Bit Description 31:20 Vertical Scale Factor UV.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 15.4.7. Overlay Color Correction Registers Used for YUV sources only. Adjustments are made before the RGB conversion. 15.4.7.1. OV0CLRC0—Overlay 0 Color Correction 0 Register Memory Address Offset: On-chip Reg. Mem Addr Offset: Default Value: Access: Size: 48h (R/W) 30148h (RO; debug path) 00h see address offset above 32 bits 31 17 16 Reserved 8 7 Contrast Bit 0 Brightness Description 31:17 Reserved. 16:8 Contrast. - 7.3F (3.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 15.4.8. Overlay Destination Color Key Registers Used for YUV sources only. Adjustments are made before the RGB conversion. 15.4.8.1. DCLRKV—Destination Color Key Value Register Memory Address Offset: On-chip Reg. Mem Addr Offset: Default Value: Access: Size: 31 24 Reserved Bit 288 50h (R/W) 30150h (RO; debug path) 00h see address offset above 32 bits 23 0 Destination Color Key Value Description 31:24 Reserved.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 15.4.8.2. DCLRKM—Destination Color Key Mask Register Memory Address Offset: On-chip Reg. Mem Addr Offset: Default Value: Access: Size: 31 30 29 Dest Color Key En Dest Const α Blend Enable Always Const α Blend Enable 54h (R/W) 30154h (RO; debug path) 00h see address offset above 32 bits 28 24 Reserved Bit 31 23 0 Destination Color Key mask Description Destination Color Key Enable.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 15.4.9. Overlay Source Color Key Registers There is an overlay source key per overlay stream, which is used on a pixel basis. The Source comparison occurs after the horizontal zooming, but in the YUV formats before the color space conversion. If the source data (overlay) is within the range, then the primary display is selected.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 15.4.9.2. SCLRKVL—Source Color Key Value Low Register Memory Address Offset: On-chip Reg. Mem Addr Offset: Default Value: Access: Size: 31 24 5Ch (R/W) 3015Ch (RO; debug path) 00h see address offset above 32 bits 23 0 Reserved Source Key value Low Bit Description 31:24 Reserved. 23:0 Source Key Value Low. In the format of the source specifies the low end (greater than or equal) of the range of excluded source pixel data.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Bit 31 Description Source Constant Alpha Blend Enable. 1 = Enable Source Alpha Blending when the logical OR of the Source Key Mask Enables are asserted within the Alpha Blend Window, and the comparison indicates that the overlay is to be displayed. 0 = Disable Source Alpha Blending. 30:27 26:24 Reserved. Source Key Mask Enables. Each bit enables one channel. If the bit is a 1, the comparison result is used; otherwise, it is ignored.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 15.4.10. Overlay Configuration Registers There is only 1 Overlay Configuration register which controls both overlay streams. It is read from memory with Overlay 0 register loads during Vertical Blank. 15.4.10.1. OV0CONF—Overlay Configuration Register Memory Address Offset: On-chip Reg.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 15.4.11. OV0CMD—Overlay Command Register Memory Address Offset: On-chip Reg. Mem Addr Offset: Default Value: Access: Size: 68h (R/W) 30168h (RO; debug path) 00h see address offset above 32 bits This register provides the data the overlay engine needs to begin work.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Bit 31 30:28 Description Select top overlay. Reserved for future implemenations Vertical Chrominance Filter. Vertical Chrominance Filter 000 = Scaling off (1:1) 001 = Line Replication 010 = Up Interpolation 011 = Reserved 100 = Reserved 101 = Pixel Dropping 110 = Down Interpolation 111 = Reserved 27:25 Vertical Luminance Filter.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Bit Description 15:14 4:2:2 Byte Order. Affects the byte order for 4:2:2 data. For other data formats these bits should be set to zero. 00 = Normal 01 = UV Swap 10 = Y Swap 11 = Y and UV swap 13:10 Source Format.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Bit 5 Description Display/Flip Type. This bit affects the buffer addressing used for buffer display and the use of the initial vertical phase. Frame mode starts addressing at the value contained in the buffer address register and increments by stride as it increments from line to line. Initial phase selection is based on the buffer and the vertical Initial phase select bit.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 15.4.12. Overlay Alpha Blend Window Position/Size Registers These registers allow for the alpha blending of a subsection of the overlay window positioning of the overlay data relative to the graphics display or the secondary display active region. It allows pixel accurate positioning. The Overlay Alpha Blend Window must be programmed to be either equal or within the Overlay Window. 15.4.12.1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 15.4.12.2. AWINSZ—Alpha Blend Window Size Register Memory Address Offset: On-chip Reg. Mem Addr Offset: Default Value: Access: Size: 31 27 Reserved 74h (R/W) 30174h (RO; debug path) 00h see address offset above 32 bits 26 Bit 15.5. 16 Alpha Blend Vertical Size 15 11 Reserved 10 0 Alpha Blend Horizontal Size Description 31:27 Reserved. 26:16 Alpha Blend Vertial Size.
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Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 16. Instruction, Memory, and Interrupt Control Registers 16.1. Instruction Control Registers 16.1.1. FENCE—Graphics Memory Fence Table Registers Address Offset: Default Value: Access: Size: 02000h – 0201Fh 00000000h Read/32 bit Write only 8x 32 bits each The Memory Hub (MH) performs address translation between linear space and tiled space.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Bit Description 31:26 Reserved for address bits 31 downto 26 25:19 Fence Lower Bound : Memory address bits 25 downto 19 (Must be size aligned) 18:15 Reserved 14:13 Reserved: MBZ (“00”) 12 Tile walk 0 = X Major 1= Y Major. 11 Reserved 10:8 Fence size: 000 = 512 KB 001 = 1 MB 010 = 2 MB 011 = 4 MB 100 = 8 MB 101 = 16 MB 110 = 32 MB 111 = Reserved.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 16.1.2. PGTBL_CTL—Page Table Control Register Address Offset: Default Value: Access: Size: 02020h 00000000h Read/Write 32 bits This register enables/disables the page table mechanism and when enabled, also sets the base address of the 4 KB aligned page table. The driver will write this register when it creates the page table at the start of virtual mode.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 16.1.3. PGTBL_ER—Page Table Error Register Address Offset: Default Value: Access: Size: 02024h (identical functionality in Device 0 at EC–EFh) 0000 0000h Read Only 32 bits This register stores information pertaining to page table error interrupts. Invalid physical address implies regions in main memory that have restricted accessibility such as PAM/SMM space etc.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Bit 2:0 Description Error Type: 000 = Invalid Table 001 = Invalid Page table entry 010 = Incorrect target for Display surface (Request to lm if the surface started in mm or vice versa)/Overlay surface (Request to lm). 011 = Invalid Miss during Display/Overlay accesses 100 = Illegal translation data (translation is valid and address points to PAM, SMM, over top and other restricted spaces in main memory). 101 = Access to local memory when not present.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 16.1.4. PGTBL_ERRMSK—Page Table Error Mask Register Address Offset: Default Value: Access: Size: 02028h (identical functionality in Device 0 at F0–F3h) 0000 0000h Read/Write 32 bits This register is new to the Intel® 815 chipset (i.e., not in the Intel® 810 chipset) The bits in this register mask out the corresponding page table error, preventing it from being reported in the Page Table Error Register.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Bit 31:9 8 Descriptions Reserved. Buffer Unit Page Table Error Mask. 0 = Not Masked (default) 1 = Masked 7 Command Streamer DMA Page Table Error Mask. 0 = Not Masked (default) 1 = Masked 6 Overlay Page Table Error Mask. 0 = Not Masked (default) 1 = Masked 5 Display Page Table Error Mask. 0 = Not Masked (default) 1 = Masked 4 Host Page Table Error Mask. 0 = Not Masked (default) 1 = Masked 3 Render Operation Page Table Error Mask.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 16.1.5. RINGBUF—Ring Buffer Registers Address Offset: 02030h – 0207Fh 02030h – 0203Fh: Low Priority Ring 02040h – 0204Fh: Interrupt Ring 02050h – 0205Fh: Reserved 02060h – 0207Fh: Reserved 00000000h Read/32 bit Write Only 4 DWords Default Value: Access: Size: Each Ring buffer is defined by a four DWord register set, which includes starting address, length, head pointer, and tail pointer. The ring buffer can be disabled when empty.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Dword Offset Bit 0 31:21 Reserved. 20:3 Tail Pointer : Programmable Qword Offset in the ring buffer (20:3 is used by the hardware). 2:0 Reserved. 31:2 Head pointer: Hardware maintained DWord Offset in the ring buffer (20:2 is used by the hardware, Bits 31:21 are incremented whenever the head pointer wraps from the end to the start of the ring buffer <> Wrap Count). 1:0 Reserved.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 16.1.6. HWS_PGA—Hardware Status Page Address Register Address Offset: Default Value: Access: Size: 02080h 1FFFF000h. Read/Write 32 bits Hardware status page physical address. The programmed address should be 4 KB aligned. Bits [11:0] are hardwired to 0. This Page will be used to report hardware status into system memory as follows. Note: For the GMCH bits 31:29 must be “0”.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 16.1.7. IPEIR—Instruction Parser Error Identification Register (debug) Address Offset: Default Value: Access: Size: 02088h 0000h Read Only 32 bits This register is used to help identify the instruction packet that generates an invalid instruction interrupt to the processor. The IPEIR will contain the origin of the offending packet. The Header will be stored in the error header register.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 16.1.9. INSTDONE—Instruction Stream Interface Done Register Address Offset: Default Value: Access: Size: 02090h FFFF FFFFh Read only. 32 bits This read only register reports engine done signals. 31 24 Reserved 23 19 Reserved 17 16 WM_Done IT_Done 15 14 13 12 11 10 9 8 CC_DONE MG_DON E DG_DON E QCC_DO NE) FTCH_DO NE MEC_DO NE MECO_D ONE CCMC_D ONE 7 6 5 4 3 2 1 0 Reserved Blitter Done Mapping Eng. Done Render Eng.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Bit Description 4 Render Engine Done 3 Batch Done 2 Reserved 1 Intr. Ring Empty or Disabled 0 Low Priority Ring Empty or Disabled 16.1.10. NOPID—NOP Identification Register Address Offset: Default Value: Access: Size: 02094h 00000000h Read Only 32 bits This register contains the value specified by the last GFXCMDPARSER_NOP_IDENTIFICATION instruction received.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 16.1.11. INSTPM—Instruction Parser Mode Register Address Offset: Default Value: Access: Size: 020C0h 00h Read/Write 8 bits The bits in this register control the operation of the Instruction Parser. Note: If an instruction type is disabled, the parser will read it out of the instruction / batch FIFO but will not send it to its destination. Error checking will be performed.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 16.1.12. INSTPS—Instruction Parser State Register (debug) Address Offset: Default Value: Access: Size: 020C4h 0000h Read Only 32 bits This register contains the state code of the Instruction Parser in the CSI. Decoding the contents of this register will indicate what the Instruction Parser is currently doing. 31 17 Reserved 15 14 CSINTR (cont.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Bit 11:10 Description CSDMA State Machine: Is responsible for the control of the DMA FIFO. It get requests from the arbitration state machine. It manages the FIFO so that requests are only made when there is space in the FIFO.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 16.1.13. BBP_PTR—Batch Buffer Parser Pointer Register (debug) Address Offset: Default Value: Access: Size: 020C8h 00000000h Read Only 32 bits This register contains the offset from the batch buffer start address of the DWord being parsed by the Instruction Parser. 31 19 18 Reserved 2 Address Offset Bit 1 0 Reserved Description 31:19 Reserved 18:2 Batch Buffer Address Pointer Offset. 1:0 Reserved 16.1.14.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 16.1.15. ABB_END—Active Batch Buffer End Address Register (debug) Address Offset: Default Value: Access: Size: 020D0h 00000000h Read Only 32 bits This register is loaded with the end address of the Batch Buffer request. The ABB_STR and ABB_END Registers will not get loaded if they are popped off of the stack.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 16.1.17. MEM_MODE—Memory Interface Mode Register (debug) Address Offset: Default Value: Access: Size: 020DCh 00000000h Read/Write 32 bits 15 8 Reserved 7 6 Other Local Cache Modes 5 4 Host Graphics Prefetch Enable 3 Reserved Bit 31:6 5 2 1 0 Reserved Graphics Address Translatio n Mode (Pg Tbl test mode) Enable Instruction FIFO Debug Mode Description Reserved.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 16.2. Interrupt Control Registers The interrupt control registers described below all share the same bit definition. The bit definition is as follows: 15 14 13 HW Detect Error Master Table 17. Reserved 12 11 10 9 8 Sync Status Toggle Pri Dply Flip Pending Reserved Overlay 0 Flip Pending Rsvd 7 6 5 4 3 2 1 0 Pri Dply VBLANK.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Bit Description 9 Overlay 0 Flip Pending. Status bit is set to reflect a pending flip when the parser parses a flip packet and cleared when the flip takes place (Display VBLANK), whereas IIR reflects Flip-Occurred# (which is contrary to the general definition of setting of IIR bits when interrupts occur). This is only affected by the use of flip packets not through the manual method or the capture auto flipping.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 16.2.1. HWSTAM—Hardware Status Mask Register Address Offset: Default Value: Access: Size: 02098h FFFFh Read/Write 16 bits This register has the same format as the Interrupt Control Registers. The corresponding bits are the mask bits that prevent that bit in the Interrupt Status Register from generating a PCI write cycle.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 16.2.2. IER—Interrupt Enable Register Address Offset: Default Value: Access: Size: 020A0h 0000h Read/Write 16 bits Individual enables for each interrupt described above. A disabled interrupt will still appear in the Interrupt Identity Register to allow polling of interrupt sources.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 16.2.3. IIR—Interrupt Identity Register Address Offset: Default Value: Access: Size: 020A4h 0000h Read/Write Clear 16 bits The individual interrupt(s), which occurred, are determined via this register. The bit is set by the interrupt event and held until cleared by writing a ‘1’ into the bit position.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 16.2.4. IMR—Interrupt Mask Register Address Offset: Default Value: Access: Size: 020A8h FFFFh Read/Write 16 bits An interrupt that is masked by this register will not appear in the Interrupt Identity Register and will not generate an interrupt. 15 14 13 HW Detect Error Master Reserved 12 11 10 9 8 Sync Status Toggle Pri Dply Flip Pending Reserved Overlay 0 Flip Pending Reserved 7 6 5 4 3 2 1 0 Pri Dply VBLANK.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 16.2.5. ISR—Interrupt Status Register Address Offset: Default Value: Access: Size: 020ACh 0100h (probably still not quite correct value) Read Only 16 bits This register contains the non-persistent value of the signals causing each interrupt. These bits are not masked by the Interrupt Mask Register. The user interrupt and the breakpoint interrupt last for one clock pulse.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 16.2.6. Error Identity, Mask and Status Registers The Error Identity, Mask, and Status registers have the following bit descriptions. The master error bit in the ISR and IIR register will be set when the OR of the unmasked (with a zero in the corresponding mask register bits) error status bits is true. 16.2.6.1. Page Table Error handling in Intel® 815 Chipset Page table errors can be caused by accessing graphics aperture space when: 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 16.2.6.2. Resetting the Page Table Error The page table error will be reset every time a write cycle is generated to bit 15 of the Interrupt Identity register (IIR), independent of the setting of the bit in the IMR or the IER. Resetting the page table error should cause the subsequent write cycles to be completed without masking of the byte enables. Note that a TLB error due to locating a page in system memory can never be cleared.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 16.2.6.3. EIR—Error Identity Register Address Offset: Default Value: Access: Size: 15 020B0h 00h Read/Write Clear 16 bits 6 Reserved 5 4 3 2 1 0 MM/LM Refresh timer error Page Table Error Display or Overlay under run Reserved Reserved Instruction Parser Error Bit 15:0 Description Error Identity Bits. (See Error Identity, Mask, and Status Register Bit Definitions table.) 1 = Error occurred 16.2.6.4.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 16.2.6.5. ESR—Error Status Register Address Offset: Default Value: Access: Size: 15 6 Reserved Bit 15:0 330 020B8h FFh Read Only 16 bits 5 4 3 2 1 0 MM/LM Refresh timer error Page Table Error Display or Overlay under run Reserved Reserved Instruction Parser Error Description Error Status Bits. (See Error Identity, Mask, and Status Register Bit Definitions table.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 16.3. Display Interface Control 16.3.1. FW_BLC—FIFO Watermark and Burst Length Control Address Offset : Default Value: Access: Size: 020D8h 22 31 73 17h Read/Write 32 bits These control values only apply to HIRes modes of operation. VGA modes ignore the settings of these registers in favor of fixed values.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Bit Description 31:28 Overlay Delay Timer1. Is used to insert waits states in between sets of YUVY requests to MM. The value in this register is multiplied by 16 to determine the wait state clock count. 27:24 Overlay Delay Timer0. Is used to insert waits states in between any two overlay streamer requests to MM except between sets of YUVY. The value in this register is multiplied by 16 to determine the wait state clock count.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 17. LCD / TV-Out Register Description During LCD or TV-Out mode, the BIOS will program the following LCD / TV-Out registers. These registers are 32-bit memory mapped. These registers are not double buffered and take effect when loaded. Further, this subsystem takes into account modified CR register values during vertical blank time for centering. This subsystem allows the timing generator to be programmed to pixel granularity.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 17.2. HBLANK—Horizontal Blank Register Address Offset: Default Value: Access: Size: 31 60004h 00000000h Read/Write 32 bits 28 27 Reserved 15 Bit 334 Horizontal Blank End 12 Reserved 16 11 0 Horizontal Blank Start Description 31:28 Reserved. 27:16 Horizontal Blank End. Horizontal blank end expressed in terms of absolute pixel number relative to the horizontal active display start.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 17.3. HSYNC—Horizontal Sync Register Address Offset: Default Value: Access: Size: 31 60008h 00000000h Read/Write 32 bits 28 27 Reserved 15 Horizontal Sync End 12 11 Reserved Bit 31:28 27:16 16 0 Horizontal Sync Start Description Reserved. Horizontal Sync End. Horizontal sync end expressed in terms of absolute pixel number relative to the horizontal active display start. Notes: 1. Minimum HSYNC width is 1 pixel clock. 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 17.4. VTOTAL—Vertical Total Register Address Offset: Default Value: Access: Size: 31 6000Ch 00000000h Read/Write 32 bits 28 27 16 Reserved 15 11 Reserved Bit 336 Vertical Total Display Pixels 10 0 Vertical Active Display Pixels Description 31:28 Reserved. 27:16 Vertical Total Display Pixels. Total vertical display lines.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 17.5. VBLANK—Vertical Blank Register Address Offset: Default Value: Access: Size: 31 60010h 00000000h Read/Write 32 bits 28 27 Reserved 15 Vertical Blank End 12 Reserved Bit 16 11 0 Vertical Blank Start Description 31:28 Reserved. 27:16 Vertical Blank End. Vertical blank end expressed in terms of absolute line number relative to the vertical active display start.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 17.6. VSYNC—Vertical Sync Register Address Offset: Default Value: Access: Size: 31 60014h 00000000h Read/Write 32 bits 28 27 Reserved 15 Vertical Sync End 12 Reserved Bit 16 11 0 Vertical Sync Start Description 31:28 Reserved. 27:16 Vertical Sync End. Vertical sync end expressed in terms of absolute line numbers relative to the vertical active display start. Notes: 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 17.7. LCDTV_C—LCD/TV-Out Control Register Address Offset: Default Value: Access: Size: 60018h 00000000h Read/Write 32 bits 31 30 29 28 27 LCD / TVOut Enable SYNC Polarity Control Centering Enable FP VESA VGA Mode 24 Reserved 23 16 Reserved 15 14 13 12 11 10 9 8 Reserved FP / 740 Data Ordering LCD Info.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Bit 28 Description FP VESA VGA Mode 0 = Disable. Use the LCD / TV Timing Generator. VGA Sync Polarity is ignored. FP Sync Polarity is used. Centering can be enabled for fixed resolution flat panels or TVs. The Flat Panel Dot clock PLL timing registers must be used for both flat panels and TVs. After these registers are written the Lock Dot Clock PLL N/M Registers must be set to 1 which makes the Dot Clock PLL only use the Flat Panel PLL registers.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Bit 8 Description FPHSYNC Output Control. 1 = Tristates the FPHSYNC pin. 0 = FPHSYNC is active unless LCD / TV Out Enable is deasserted. 7 Border Enable. 1 = Border to the LCD / TV encoder is enabled. 0 = Border to the LCD / TV encoder is disabled. 6 Active Data Order. 1 = Reversed ½ pixel data ordering: G[3:0] ‘ B[7:0] followed by R[7:0] ‘ G[7:4]. 0 = Normal ½ pixel data ordering: R[7:0] ‘ G[7:4] followed by G[3:0] ‘ B[7:0].
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 17.8. OVRACT—Overlay Active Register Address Offset: Default Value: Access: Size: 6001Ch 00000000h Read/Write 32 bits 31 27 26 16 Reserved 15 12 Overlay Active End 11 0 Reserved Overlay Active Start Bit 17.9. Description 31:27 Reserved. 26:16 Overlay Active End. This filed takes into account the Overlay pipeline delays for turning off the overlay at the end of a scan line.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 18. Local Memory Interface 18.1. DRT—DRAM Row Type Address offset : Default value : Access : Size : 03000h 00h Read / write 8 bit This 8-bit register identifies whether or not the local memory is populated. 7 1 Reserved Bit 7:1 0 0 DRAM Populated Description Reserved DRAM Populated (DP).
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 18.2. DRAMCL—DRAM Control Low Address offset : Default value : Access : Size : 03001h 17h Read / write 8 bit 7 5 Reserved 4 3 2 1 0 Paging Mode Control RAS-toCAS Override CAS# Latency RAS# Riming RAS# Precharge Timing Bit 7:5 4 Description Reserved Paging Mode Control (PMC). 0 = Page Open Mode. In this mode the GMCH memory controller tends to leave pages open. 1 = Page Close Mode.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 18.3. DRAMCH—DRAM Control High Address offset : Default value : Access : Size : 7 03002h 08h Read / write 8 bit 5 Reserved Bit 4 3 DRAM Refresh Rate 2 0 Special Mode Select Description 7:5 Reserved 4:3 DRAM Refresh Rate (DRR). DRAM refresh is controlled using this field. Disabling refresh results in the eventual loss of DRAM data, although refresh can be briefly disabled without data loss.
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Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 19. I/O Control Registers 19.1. HVSYNC—HSYNC/VSYNC Control Register Address Offset: Default Value: Size: Attribute: 05000h 00000000h 32 bits R/W Bits 19:16 are for DPMS and DDC Sync Select. DPMS MODE HSYNC/VSYNC Control[19:16] Power On 0000 (i.e., pulse H and V) StandBye 0010 (i.e., pulse V) Suspend 1000 (i.e.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 19.2. GPIO Registers 19.2.1. GPIOA General Purpose I/O Control Register A Address offset : Default value : Access : Size : 05010h 00h, 00h, 000U0000b, 000U0000b Read / write 32 bit This register controls the general purpose I/O pins DDCK and DDDA, which are used to create a Display Data Channel (DDC) serial bus for communication with an external analog display monitor.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Bit Description 8 DDDA Direction Mask—R/W: This is a mask bit to determine whether the GPIO DIRECTION VALUE bit should be written into the register. 0 = Do NOT write DDDA Direction Value bit (default). 1 = Write DDDA Direction Value bit. 7:5 4 Reserved DDCK Data In—RO: This is the value that is sampled on the DDCK pin as an input.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 19.2.2. GPIOB General Purpose I/O Control Register B Address offset : Default value : Access : Size : 05014h 00h, 00h, 000U0000b, 000U0000b Read / write 32 bit This register controls the general purpose I/O pins LTVCK and LTVDA, which are used to create an I2C connection to the external Digital Video Out controller.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Bit 8 Description LTVDA Direction Mask—R/W: This is a mask bit to determine whether the GPIO DIRECTION VALUE bit should be written into the register. 0 = Do NOT write LTVDA Direction Value bit (default). 1 = Write LTVDA Direction Value bit. 7:5 4 Reserved. LTVCK Data In—RO: This is the value that is sampled on the LTVCK pin as an input.
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Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 20. Display And Cursor Registers The following are cursor, display, and pixel pipe registers in address range 70000h–7FFFFh. 20.1. DISP_SL—Display Scan Line Count Memory Offset Address: Default: Attributes: 70000h 0000h Read only This register enables the read back of the display vertical line counter. In interlaced display modes the line counter is initialized to the field and is incremented by two at each HSYNC.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 20.2. DISP_SLC—Display Scan Line Count Range Compare Memory Offset Address: Default: Attributes: 70004h 0000h Read only The Top and Bottom Line Count Compare registers are compared with the display line values from CRTTG (the CRT timing generator) or the TV/FP timing generator, depending upon whether the TV/FP timing generator is enabled and not in FP VESA VGA Mode (LCDTV_C[31]=1 AND LCDTV_C[28]=0) or not.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 20.3. Pixel Pipeline Control 20.3.1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Bit 19:16 Descriptions Display Color Mode. 0000 = CRT standard VGA text and graphics mode and 1-bit/2-bit/4-bit packed graphics mode (Default). 0001 = Reserved. 0010 = CRT 8-bit packed extended graphics mode. 0011 = Reserved. 0100 = CRT 16-bit packed (5-5-5) extended graphics mode (Targa compatible). 0101 = CRT 16-bit packed (5-6-5) extended graphics mode (XGA compatible). 0110 = CRT 24-bit extended graphics mode compressed.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Bit Descriptions 0 GUI Mode. 0 = Standard VGA and extended 4 bpp/16 color resolutions (default). Can still access memory in linear mode. 1 = High Resolution (i.e., not VGA or extended planar).
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 20.3.4. DPLYBASE—Display Base Address Register Memory Offset Address: Default: Attributes: 70020h 0000h Read/Write The display can be read from graphics memory. This register is the display staging register when written. The load register is transferred into the active register on the asserting edge of Vertical Sync. The read back register is from the active register.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 20.3.5. DPLYSTAS—Display Status Select Register Memory Offset Address: Default: Attributes: 70024h 0000h Read/Write This register selects the proper events to be signaled to the Interrupt Control Register in the command stream. Status bits 0 and 1 are logically ORed to become the Vertical Blank status bit and status bits 8, 9, and 10 are logically ORed to become the Display Event status bit.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Bit 23:18 17 Descriptions Reserved. Vertical Blank Enable. 0 = Vertical Blank Status Disabled 1 = Vertical Blank Status Enabled 16 Overlay Registers Upated Enable. 0 = Overlay Registers have been updated during Vertical Blank Status Disabled 1 = Overlay Registers have been updated during Vertical Blank Status Enabled 15 Flat Panel Hot Plug Detect Status. This bit is the state of the TVCLKIN pin of the TV/Flat Panel interface.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 20.4. Hardware Cursor The hardware cursor registers are memory mapped and accessible through 32 bit accesses. 20.4.1. CURCNTR—Cursor Control Register Memory Offset Address: Default: Attributes: 70080h 0000h Read/Write This register is double buffered. The load register is transferred into the active register on the asserting edge of Vertical Sync.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 20.4.2. CURBASE—Cursor Base Address Register Memory Offset Address: Default: Attributes: 70084h 0000h Read/Write The cursor can only be read from System memory. This register is double buffered. The load register is transferred into the active register on the asserting edge of Vertical Sync. 31 29 28 Reserved 8 Cursor Base Address Bits [28:08] Bit 20.4.3. 7 0 Reserved Descriptions 31:29 Reserved. 28:8 Cursor Base Address Bits [28:08].
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R 21. Appendix A: Mode Parameters This appendix contains the register programming information on a per-mode basis. Refer to the appropriate table for the specific values to use in order to correctly program the graphics adapter for the desired mode and frequency combination. Programming the graphics adapter with values not included in these tables may damage the adapter and any connected output devices.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Parameters for Screen Resolution/Refresh Rate: 364 320x200_70Hz = Dot Clock Value 25 // 25.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Parameters for Screen Resolution/Refresh Rate: 366 352X480_70Hz = Dot Clock Value 15 //15.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Parameters for Screen Resolution/Refresh Rate: 370 640x350_85Hz = Dot Clock Value 31 //31.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Parameters for Screen Resolution/Refresh Rate: 640x400_70Hz = Dot Clock Value 25 //25.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Parameters for Screen Resolution/Refresh Rate: 372 640x400_85Hz = Dot Clock Value 31 //31.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Parameters for Screen Resolution/Refresh Rate: 640x480_60Hz = Dot Clock Value 25 //25.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Parameters for Screen Resolution/Refresh Rate: 640x480_72Hz = Dot Clock Value 31 //31.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Parameters for Screen Resolution/Refresh Rate: 376 640x480_75Hz = Dot Clock Value 31 //31.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Parameters for Screen Resolution/Refresh Rate: 378 720x400_85Hz = Dot Clock Value 35 //35.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Parameters for Screen Resolution/Refresh Rate: 720x480_60Hz = Dot Clock Value 28 //28.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Parameters for Screen Resolution/Refresh Rate: 384 720x576_85Hz = Dot Clock Value 49 //49.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Parameters for Screen Resolution/Refresh Rate: 800x600_75Hz = Dot Clock Value 49 //49.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Parameters for Screen Resolution/Refresh Rate: 390 800x600_85Hz = Dot Clock Value 56 //56.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Parameters for Screen Resolution/Refresh Rate: 392 854X480_75Hz = Dot Clock Value 41 //41.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Parameters for Screen Resolution/Refresh Rate: 396 1024X768_75Hz = Dot Clock Value 78 //78.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Parameters for Screen Resolution/Refresh Rate: 1024X768_85Hz = Dot Clock Value 94 //94.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Parameters for Screen Resolution/Refresh Rate: 408 1280x960_85Hz = Dot Clock Value 148 //148.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Parameters for Screen Resolution/Refresh Rate: 410 1280x1024_70Hz = Dot Clock Value 129 //128.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Parameters for Screen Resolution/Refresh Rate: 1280x1024_85Hz = Dot Clock Value 157 //157.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Parameters for Screen Resolution/Refresh Rate: 418 1600x1200_65Hz = Dot Clock Value 175 //175.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Parameters for Screen Resolution/Refresh Rate: 1600x1200_75Hz = Dot Clock Value 202 //202.
Intel® 815 Chipset: Graphics Controller PRM, Rev 1.0 R Parameters for Screen Resolution/Refresh Rate: 422 1600x1200_85Hz = Dot Clock Value 229 //229.
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