815 Chipset Platform Owner Manual

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Intel

815 Chipset Platform

For Use with Universal Socket 370

Design Guide

April 2001

Document Number: 298349-001

Summary of content (213 pages)

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R Intel® 815 Chipset Platform For Use with Universal Socket 370 Design Guide April 2001 Document Number: 298349-001
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R ® Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
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R Contents Introduction ........................................................................................................................13 1 1.1 1.2 1.3 2 Terminology ..........................................................................................................14 Reference Documents ..........................................................................................16 System Overview ..............................................................................................
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R 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 6 System Memory Design Guidelines...................................................................................69 6.1 6.2 6.3 6.4 6.5 7 System Memory Routing Guidelines.....................................................................69 System Memory 2-DIMM Design Guidelines ........................................................70 6.2.1 System Memory 2-DIMM Connectivity ..................................................70 6.2.
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R 7.4 7.5 7.6 7.7 7.8 7.9 8 7.3.2.2 AGP-Only Motherboard Guidelines......................................86 7.3.3 AGP Routing Guideline Considerations and Summary.........................87 7.3.4 AGP Clock Routing ...............................................................................88 7.3.5 AGP Signal Noise Decoupling Guidelines.............................................88 7.3.6 AGP Routing Ground Reference...........................................................
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R 10.3 10.4 10.5 10.6 10.7 10.8 10.9 11 Clocking ...........................................................................................................................131 11.1 11.2 11.3 11.4 11.5 11.6 11.7 12 12.2 12.3 12.4 Thermal Design Power .......................................................................................144 12.1.1 Pull-Up and Pull-Down Resistor Values ..............................................144 ATX Power Supply PWRGOOD Requirements...............................
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R 13.4 13.5 13.6 13.7 13.8 13.9 13.10 14 13.3.1 AGP Interface 1X Mode Checklist.......................................................158 13.3.2 Designs That Do Not Use the AGP Port .............................................159 13.3.3 System Memory Interface Checklist....................................................160 13.3.4 Hub Interface Checklist .......................................................................160 13.3.5 Digital Video Output Port Checklist .................................
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R Figures Figure 1. System Block Diagram .......................................................................................17 Figure 2. GMCH Block Diagram ........................................................................................18 Figure 3. Board Construction Example for 60 Ω Nominal Stackup ...................................25 Figure 4. GMCH 544-Ball µBGA* CSP Quadrant Layout (Top View)................................27 Figure 5. ICH 241-Ball µBGA* CSP Quadrant Layout (Top View)......
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R Figure 49. Schematic of RAMDAC Video Interface.........................................................102 Figure 50. Cross-Sectional View of a Four-Layer Board .................................................103 Figure 51. Recommended RAMDAC Component Placement & Routing........................104 Figure 52. Recommended RAMDAC Reference Resistor Placement and Connections 105 Figure 53. Hub Interface Signal Routing Example ..........................................................107 Figure 54.
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R Tables Table 1. Processor Considerations for Universal Socket 370 Design...............................29 Table 2. GMCH Considerations for Universal Socket 370 Design ....................................30 Table 3. ICH Considerations for Universal Socket 370 Design .........................................30 Table 4. Clock Synthesizer Considerations for Universal Socket 370 Design ..................31 Table 5. Determining the Installed Processor via Hardware Mechanisms ........................
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R Revision History Rev. No. -001 ® Description Initial Release.
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Introduction R 1 Introduction This design guide organizes Intel’s design recommendations for the Intel® 815 chipset platform for use with the Universal Socket 370. In addition to providing motherboard design recommendations (e.g., layout and routing guidelines), this document also addresses system design issues (e.g., thermal requirements). This document contains design recommendations, board schematics, debug recommendations, and a system checklist.
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Introduction R 1.1 Terminology This section describes some of the terms used in this document. Additional power delivery term definitions are provided at the beginning of Chapter 12, Power Delivery. Term Description Aggressor A network that transmits a coupled signal to another network is called the aggressor network. Aggressor A network that transmits a coupled signal to another network is called the aggressor network.
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Introduction R Term ® Description Ringback The voltage that a signal rings back to after achieving its maximum absolute value. Ringback may be due to reflections, driver oscillations, or other transmission line phenomena. Setup Window The time between the beginning of Setup to Clock (TSU_MIN) and the arrival of a valid clock edge. This window may be different for each type of bus agent in the system.
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Introduction R 1.2 Reference Documents Document Document Number / Location Intel® 815 Chipset Family: 82815 Graphics and Memory Controller Hub (GMCH) for use with the Universal Socket 370 Datasheet 298351 Intel® 82802AB/82802AC Firmware Hub (FWH) Datasheet 290658 ® Intel 82801AA (ICH) and 82801AB (ICH0) I/O Controller Hub Datasheet 290655 ® 243341 ® (http://developer.intel .
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Introduction R elimination of ISA provides true plug-and-play for the platform. Traditionally, the ISA interface was used for audio and modem devices. The addition of AC’97 allows the OEM to use softwareconfigurable AC’97 audio and modem coder/decoders (codecs), instead of the traditional ISA devices. 1.3.
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Introduction R 1.3.2 Component Features Figure 2. GMCH Block Diagram System bus (66/100/133 MHz) Processor I/F SDRAM 100/133 MHz, 64 bit System memory I/F Primary display GPA or AGP 2X/4X card AGP I/F Local memory I/F Data stream control & dispatch Overlay H/W cursor RAMDAC Monitor FP / TVout Digital video out 3D pipeline 2D (blit engine) Internal graphics Hub I/F Hub comp_blk_1 1.3.2.
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Introduction R • Accelerated Graphics Port (AGP) Interface  Supports AGP 2.0, including 4X AGP data transfers, but not the 2X/4X Fast Write protocol  AGP universal connector support via dual-mode buffers to allow AGP 2.0 3.3V or 1.
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Introduction R 1.3.2.2 Intel® 82801AA I/O Controller Hub (ICH) The I/O Controller Hub provides the I/O subsystem with access to the rest of the system, as follows: • • • • • • • • • • • • Upstream accelerated hub architecture interface for access to the GMCH PCI 2.2 interface (6 PCI Request/Grant pairs) Bus master IDE controller; supports Ultra ATA/66 USB controller I/O APIC SMBus controller FWH interface LPC interface AC’97 2.
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Introduction R 1.3.3 Platform Initiatives 1.3.3.1 Universal Socket 370 Design The Intel 815 chipset platform for use with the Universal Socket 370 allows systems designers to build one system that is compatible with the Pentium III processor (CPUID=068xh), Celeron processor (CPUID=068xh), and future 0.13 micron socket 370 processors. When implemented, the Intel 815 chipset platform for use with the Universal Socket 370 can detect which processor is present in the socket and function accordingly. 1.3.3.
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Introduction R 1.3.3.6 Manageability The Intel 815 chipset platform integrates several functions designed to manage the system and lower the system’s total cost of ownership (TCO) of the system. These system management functions are designed to report errors, diagnose the system, and recover from system lock-ups, without the aid of an external microcontroller. TCO Timer The ICH integrates a programmable TCO Timer. This timer is used to detect system locks.
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Introduction R 1.3.3.7 AC’97 The Audio Codec ’97 (AC’97) specification defines a digital interface that can be used to attach an audio codec (AC), a modem codec (MC), an audio/modem codec (AMC) or both an AC and an MC. The AC’97 specification defines the interface between the system logic and the audio or modem codec, known as the AC’97 Digital Link.
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General Design Considerations R 2 General Design Considerations This document provides motherboard layout and routing guidelines for systems based on the Intel 815 chipset platform for use with the Universal Socket 370. The document does not discuss the functional aspects of any bus or the layout guidelines for an add-in device. If the guidelines listed in this document are not followed, it is very important that thorough signal integrity and timing simulations be completed for each design.
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Component Quadrant Layouts R 3 Component Quadrant Layouts Figure 4 illustrates the relative signal quadrant locations on the GMCH ballout. It does not represent the actual ballout. Refer to the Intel® 815 Chipset Family: 82815 Graphics and Memory Controller Hub (GMCH) for use with the Universal Socket 370 Datasheet for the actual ballout. Figure 4.
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Component Quadrant Layouts R Figure 5 illustrates the relative signal quadrant locations on the ICH ballout. It does not represent the actual ballout. Refer to the Intel® 82801AA (ICH) and 82801AB (ICH0) I/O Controller Hub Datasheet for the actual ballout. Figure 5. ICH 241-Ball µBGA* CSP Quadrant Layout (Top View) Pin 1 corner PCI Processor ICH Hub interface AC'97, SMBus IDE LPC quad_ICH Figure 6.
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Universal Socket 370 Design R 4 Universal Socket 370 Design 4.1 Universal Socket 370 Definitions The universal socket 370 platform supports Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh) as well as future 0.13 micron socket 370 processors. The Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh) have different requirements for functioning properly in a platform than the future 0.13 micron socket 370 processors.
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Universal Socket 370 Design R Signal Name or Pin Number Function In Intel® Pentium® III Processor (CPUID=068xh) and Intel® Celeron™ Processor (CPUID=068xh) Function In Future 0.13 Micron Socket 370 Processors Implementation for Universal Socket 370 Design PWRGOOD Requires 2.5V Requires 1.8V Addition of resistor-divider network to provide 2.1V, which will satisfy voltage tolerance requirements of the Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh) as well as future 0.
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Universal Socket 370 Design R Table 4. Clock Synthesizer Considerations for Universal Socket 370 Design Signal VDD Issue Implementation For Universal Socket 370 Design Intel® CK-815 does not support VTTPWRGD Addition of FET switch which supplies power to VDD only when VTTPWRGD is asserted. Note: FET must have no more than 100 milliohms resistance between source and drain. 4.2 Processor Design Requirements 4.2.
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Universal Socket 370 Design R 4.2.2 Identifying the Processor at the Socket For the platform to configure for the requirements of the processor in the socket, it must first identify whether the processor is a Pentium III processor (CPUID=068xh) / Celeron processor (CPUID=068xh), or a future 0.13 micron socket 370 processors. Pin AF36 is a ground pin on a Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh); pin AF36 is an unconnected pin on future 0.13 micron Socket 370 processors.
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Universal Socket 370 Design R 4.2.3 Setting the Appropriate Processor VTT Level Because the Pentium III processor (CPUID=068xh) / Celeron processor (CPUID=068xh), and future 0.13 micron socket 370 processors require different VTT levels, the platform must be able to provide the appropriate voltage level after determining which processor is in the socket.
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Universal Socket 370 Design R 4.2.4 VTT Processor Pin AG1 Processor pin AG1 requires additional attention since it is a ground pin on a Pentium III processor (CPUID=068xh) / Celeron processor (CPUID=068xh) and a VTT pin on a future 0.13 micron socket 370 processor. A separate switch controlled by the TUAL5 reference schematic signal determines whether pin AG1 is pulled to ground or VTT. Refer to Figure 10 for an example implementation. Figure 10.
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Universal Socket 370 Design R Figure 11. Processor Identification Strap on GMCH SMAA[12] 10 K Ω TUAL5 Proc_ID_Strap Table 5 provides the logic decoding to determine which processor is installed in a PGA370 design. Table 5. Determining the Installed Processor via Hardware Mechanisms ® Processor Pin AF36 CPUPRES# Hi-Z 0 Future 0.13 micron socket 370 processor installed. Low 0 Intel® Pentium® III processor (CPUID=068xh) or Intel® Celeron™ processor (CPUID=068xh) installed.
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Universal Socket 370 Design R 4.2.6 Configuring Non-VTT Processor Pins When asserted, the VTTPWGRD signal must be level-shifted to 12V to properly drive the gating circuitry of the Intel® CK-815. Furthermore, while the VTTPWRGD signal is connected to the VTTPWRGD pin on a future 0.13 micron socket 370 processor, on a Pentium III processor (CPUID=068xh) or Celeron processor (CPUID=068xh) that same pin is a ground. To provide proper functionality, a 1.
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Universal Socket 370 Design R 4.2.7 VCMOS Reference In previous platforms supporting the Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh), VCMOS was generated by the processor itself. The future 0.13 micron socket 370 processors do not generate VCMOS, and the universal platform is required to generate this separately on the motherboard.
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Universal Socket 370 Design R 4.2.8 Processor Signal PWRGOOD The processor signal PWRGOOD is specified at different voltage levels depending on whether it is a Pentium III processor (CPUID=068xh) / Celeron processor (CPUID=068xh), or whether it is a future 0.13 micron socket 370 processor. As there is an overlap between the ranges of accepted voltage levels for these two processor groups, a resistor divider network that provides 2.1V will satisfy the requirements of all supported processors.
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Universal Socket 370 Design R 4.2.9 APIC Clock Voltage Switching Requirements The processor’s APIC clock is also specified at different voltage levels depending on whether it is for the Pentium III processor (CPUID=068xh) / Celeron processor (CPUID=068xh) or whether it is for a future 0.13 micron socket 370 processor. There is no overlap in the range of accepted voltage levels for the two processor groups, so a voltage switch is required to ensure proper operation.
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Universal Socket 370 Design R 4.2.10 GTLREF Topology and Layout In a platform supporting the future 0.13 micron socket 370 processors, the voltage requirements for GTLREF are different for the processor and the chipset. The GTLREF on the processor is specified to be 2/3 * VTT, while the GTLREF on the chipset is 0.7 * VTT. This difference requires that separate resistor sites be added to the layout to split the GTLREF sources.
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Universal Socket 370 Design R 4.3 Power Sequencing on Wake Events In addition to the mechanism for identifying the processor in the socket, special handling of wake events is required for the Intel 815 chipset platform that support functionality of the future 0.13 micron socket 370 processors. When a wake event is triggered, the GMCH and the Intel CK-815 must not sample BSEL[1:0] until the signal VTTPWRGD is asserted. This is handled by setting up the following sequence of events: 1.
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Universal Socket 370 Design R 4.3.2 Gating of PWROK to ICH With power being gated to the Intel CK-815 by the signal VTTPWRGD12, it is important that the clocks to the ICH are stable before the power supply asserts PWROK to the ICH. As the clocking power gating circuitry relies on the 12V supply, there is no guarantee that these conditions will be met.
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System Bus Design Guidelines R 5 System Bus Design Guidelines The Pentium III processor delivers higher performance by integrating the Level-2 cache into the processor and running it at the processor’s core speed. The Pentium III processor runs at higher core and system bus speeds than previous-generation Intel® IA-32 processors while maintaining hardware and software compatibility with earlier Pentium III processors.
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System Bus Design Guidelines R ® ® Table 6. Intel Pentium III Processor AGTL/AGTL+ Parameters for Example Calculations IC Parameters Intel® Pentium® III Processor at 133 MHz System Bus GMCH Notes Clock to Output maximum (TCO_MAX) • 3.25 ns (for 66/100/133 MHz system bus speeds) 4.1 ns 1, 2 Clock to Output minimum (TCO_MIN) • 0.40 ns (for 66/100/133 MHz system bus) 1.05 ns 1, 2 Setup time (TSU_MIN) • 1.20 ns (for BREQ Lines) 2.65 ns 1, 2,3 0.10 ns 1 • 0.
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System Bus Design Guidelines R Table 7. Example TFLT_MAX Calculations for 133 MHz Bus Driver 1 2 Receiver Clk Period TCO_MAX TSU_MIN ClkSKEW ClkJITTER MADJ Recommended TFLT_MAX Processor GMCH 7.50 3.25 2.65 0.20 0.25 0.40 1.1 GMCH Processor 7.50 4.1 1.20 0.20 0.25 0.40 1.35 NOTES: 1. All times in nanoseconds 2. BCLK period = 7.50 ns at 133.33 MHz Table 8.
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System Bus Design Guidelines R 5.2 General Topology and Layout Guidelines Figure 19. Topology for 370-Pin Socket Designs with Single-Ended Termination (SET) PGA370 socket G MCH L(1): Z 0 = 60 Ω ± 15% sys_bus_topo_PGA370 Table 9. Trace Guidelines for Figure 19 1, 2, 3 Description Min. Length (inches) Max. Length (inches) 1.90 4.50 GMCH to PGA370 socket trace NOTES: 1. All AGTL/AGTL+ bus signals should be referenced to the ground plane for the entire route. 2.
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System Bus Design Guidelines R 5.2.1 Motherboard Layout Rules for AGTL/AGTL+ Signals Ground Reference It is strongly recommended that AGTL/AGTL+ signals be routed on the signal layer next to the ground layer (referenced to ground). It is important to provide an effective signal return path with low inductance. The best signal routing is directly adjacent to a solid GND plane with no splits or cuts. Eliminate parallel traces between layers not separated by a power or ground plane.
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System Bus Design Guidelines R Minimizing Cross-Talk The following general rules minimize the impact of cross-talk in a high-speed AGTL/AGTL+ bus design: • Maximize the space between traces. Where possible, maintain a minimum of 10 mils (assuming a 5-mil trace) between trace edges. It may be necessary to use tighter spacing when routing between component pins.
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System Bus Design Guidelines R 5.2.1.1 Motherboard Layout Rules for Non-AGTL/AGTL+ (CMOS) Signals Table 11.
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System Bus Design Guidelines R 5.2.1.2 THRMDP and THRMDN These traces (THRMDP and THRMDN) route the processor’s thermal diode connections. The thermal diode operates at very low currents and may be susceptible to cross-talk. The traces should be routed close together to reduce loop area and inductance. Figure 21. Routing for THRMDP and THRMDN Signal Y 1 — Maximize (min. – 20 mils) THRMDP 2 — Minimize THRMDN 1 — Maximize (min. – 20 mils) Signal Z bus_routing_thrmdp-thrmdn NOTES: 1.
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System Bus Design Guidelines R 5.3 Electrical Differences for Universal PGA370 Designs There are several electrical changes between previous PGA370 designs and the universal PGA370 design, as follows: • Changes to the PGA370 socket pin definitions. • Addition of VTTPWRGD signal to ensure stable VID selection for future 0.13 micron socket 370 processors. • Addition of THERMTRIP circuit to allow processor to detect catastrophic overheat. • Addition of VID[25 mV] signal to support future 0.
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System Bus Design Guidelines R 5.4 PGA370 Socket Definition Details The following table compares the pin names and functions of the Intel processors supported in the Intel 815 chipset platform for use with the universal socket 370. Table 12. Processor Pin Definition Comparison Pin # Pin Name Intel® Celeron™ Processor (CPUID=068xh) Pin Name Intel® Pentium® III Processor (CPUID=068xh) Pin Name Future 0.
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System Bus Design Guidelines R Pin # Pin Name Intel® Celeron™ Processor (CPUID=068xh) Pin Name Intel® Pentium® III Processor (CPUID=068xh) Pin Name Future 0.13 Micron Socket 370 Processors AJ31 VSS VSS RESET Function • Ground for Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh). • RESET for future 0.13 micron socket 370 processors AK4 VSS VSS VTTPWRGD • Ground for Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh). • VID control signal on future 0.
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System Bus Design Guidelines R Pin # Pin Name Intel® Celeron™ Processor (CPUID=068xh) Pin Name Intel® Pentium® III Processor (CPUID=068xh) Pin Name Future 0.13 Micron Socket 370 Processors Function E23 Reserved VTT VTT • AGTL/AGTL+ termination voltage G35 Reserved VTT VTT • AGTL/AGTL+ termination voltage G37 Reserved Reserved VTT • Reserved for Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh). • AGTL termination voltage for future 0.
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System Bus Design Guidelines R Pin # Pin Name Intel® Celeron™ Processor (CPUID=068xh) Pin Name Intel® Pentium® III Processor (CPUID=068xh) Pin Name Future 0.13 Micron Socket 370 Processors Y1 Reserved Reserved NC Function • Reserved for Pentium III processor (CPUID=068xh) and Celeron processor (CPUID=068xh). • No connect for future 0.13 micron socket 370 processors Y33 Reserved CLKREF CLKREF Z362 VCC2.5 VCC2.5 NC • 1.25V PLL reference • VCC2.
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System Bus Design Guidelines R 5.5 BSEL[1:0] Implementation Differences A future 0.13 micron socket 370 processor will select the 133 MHz system bus frequency setting from the clock synthesizer. A Pentium III processor (CPUID=068xh) utilizes the BSEL1 pin to select either the 100 MHz or 133 MHz system bus frequency setting from the clock synthesizer. An Celeron processor (CPUID=068xh) will use both BSEL pins to select 66 MHz system bus frequency from the clock synthesizer.
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System Bus Design Guidelines R 5.6 CLKREF Circuit Implementation The CLKREF input (used by the Pentium III processor (CPUID=068xh), Celeron processor (CPUID=068xh), and future 0.13 micron socket 370 processors) requires a 1.25V source. It can be generated from a voltage divider on the VCC2.5 or VCC3.3 sources using 1% tolerant resistors. A 4.7 µF decoupling capacitor should be included on this input. See Figure 24 and Table 13 for example CLKREF circuits.
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System Bus Design Guidelines R 5.8 Processor Reset Requirements Universal PGA370 designs must route the AGTL/AGTL+ reset signal from the chipset to two pins on the processor as well as to the debug port connector. This reset signal is connected to the following pins at the PGA370 socket: • AH4 (RESET#). The reset signal is connected to this pin for the Pentium III processor (CPUID=068xh), Celeron processor (CPUID=068xh), and future 0.
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System Bus Design Guidelines R 5.9 Processor PLL Filter Recommendations Intel PGA370 processors have internal phase lock loop (PLL) clock generators that are analog and require quiet power supplies to minimize jitter. 5.9.1 Topology The general desired topology for these PLLs is shown in Figure 27. Not shown are the parasitic routing and local decoupling capacitors. Excluded from the external circuitry are parasitics associated with each component. 5.9.
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System Bus Design Guidelines R Figure 26. Filter Specification 0.2dB 0dB -0.5 dB Forbidden Zone Forbidden Zone -28dB -34dB DC 1Hz fpeak 1 MHz passband 66 MHz fcore high frequency band filter_spec NOTES: 1. Diagram not to scale. 2. No specification for frequencies beyond fcore. 3. fpeak should be less than 0.05 MHz. Other requirements: • Use shielded-type inductor to minimize magnetic pickup. • Filter should support DC current > 30 mA.
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System Bus Design Guidelines R 5.9.3 Recommendation for Intel Platforms The following tables contain examples of components that meet Intel’s recommendations, when configured in the topology of Figure 27. Table 15. Component Recommendations – Inductor Part Number Value Tol. SRF Rated Current DCR (Typical) TDK MLF2012A4R7KT 4.7 µH 10% 35 MHz 30 mA 0.56 Ω (1 Ω max.) Murata LQG21N4R7K00T1 4.7 µH 10% 47 MHz 30 mA 0.7 Ω (± 50%) Murata LQG21C4R7N00 4.7 µH 30% 35 MHz 30 mA 0.3 Ω max.
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System Bus Design Guidelines R Figure 27. Example PLL Filter Using a Discrete Resistor VCC CORE R L <0.1 Ω route PLL1 Discrete resistor Processor C <0.1 Ω route PLL2 PLL_filter_1 Figure 28. Example PLL Filter Using a Buried Resistor VCC CORE R L <0.1 Ω route PLL1 T race resistance Processor C <0.
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System Bus Design Guidelines R 5.9.4 Custom Solutions As long as designers satisfy filter performance and requirements as specified and outlined in Section 5.9.2, other solutions are acceptable. Custom solutions should be simulated against a standard reference core model (see Figure 29). Figure 29. Core Reference Model PLL1 Processor 0.1 Ω 120 pF PLL2 1 kΩ 0.1 Ω sys_bus_core_ref_model NOTES: 1. 0.1 Ω resistors represent package routing. 2. 120 pF capacitor represents internal decoupling capacitor.
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System Bus Design Guidelines R Figure 30. Capacitor Placement on the Motherboard 5.11.2 VTT Decoupling Design For Itt = 2.3 A (maximum) • Twenty 0.1 µF capacitors in 0603 packages placed as closed as possible to the processor VTT pins. The capacitors are shown on the exterior of the previous figure. 5.11.3 VREF Decoupling Design • Four 0.1 µF capacitors in 0603 package placed near VREF pins (within 500 mils).
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System Bus Design Guidelines R 5.12 Thermal Considerations 5.12.1 Heatsink Volumetric Keepout Regions Current heatsink recommendations are only valid for supported Celeron and Pentium III processor frequencies. Figure 31 shows the system component keepout volume above the socket connector required for the reference design thermal solution for high frequency processors.
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System Bus Design Guidelines R Figure 31. Heatsink Volumetric Keepout Regions Figure 32.
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System Bus Design Guidelines R 5.13 Debug Port Changes Due to the lower voltage technology employed with newer processors, changes are required to support the debug port. Previously, test access port (TAP) signals used 2.5V logic, as is the case with the Intel Celeron processor in the PPGA package. Pentium III processor (CPUID=068xh), Celeron processor (CPUID=068xh), and future 0.13 micron socket 370 processors utilize 1.5V logic levels on the TAP.
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System Memory Design Guidelines R 6 System Memory Design Guidelines 6.1 System Memory Routing Guidelines Ground plane reference all system memory signals. To provide a good current return path and limit noise on the system memory signals, the signals should be ground referenced from the GMCH to the DIMM connectors and from DIMM connector-to-DIMM connector. If ground referencing is not possible, system memory signals should be, at a minimum, referenced to a single plane.
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System Memory Design Guidelines R 6.2 System Memory 2-DIMM Design Guidelines 6.2.1 System Memory 2-DIMM Connectivity Figure 35. System Memory Connectivity (2 DIMM) Double-Sided, Unbuffered Pinout without ECC SCSA[3:2]# SCSA[1:0]# SCKE[1:0] Notes: Min. (16 Mbit) 8 MB Max. (64 Mbit) 256 MB Max.
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System Memory Design Guidelines R 6.2.2 System Memory 2-DIMM Layout Guidelines Figure 36. System Memory 2-DIMM Routing Topologies 82815 DIMM 0 Topology 1 A Topology 2 C Topology 3 D Topology 4 F 10 Ω E Topology 5 B 10 Ω E DIMM 1 F sys_mem_2DIMM_routing_topo Table 18. System Memory 2-DIMM Solution Space Signal Top. Trace (mils) Trace Lengths (inches) A Width Spacing Min. B Max. Min. C Max. Min. D Max. E Min. Max. 1 4.5 F Min. Max. Min. Max.
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System Memory Design Guidelines R Figure 37. System Memory Routing Example sys_mem_routing_ex NOTE: 72 Routing in this figure is for example purposes only. It does not necessarily represent complete and correct routing for this interface.
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System Memory Design Guidelines R 6.3 System Memory 3-DIMM Design Guidelines 6.3.1 System Memory 3-DIMM Connectivity Figure 38. System Memory Connectivity (3 DIMM) Double-Sided, Unbuffered Pinout without ECC SCSA[5:4]# SCSA[3:2]# SCSA[1:0]# Notes: Min. (16 Mbit) 8 MB Max. (64 Mbit) 256 MB Max.
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System Memory Design Guidelines R 6.3.2 System Memory 3-DIMM Layout Guidelines Figure 39.
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System Memory Design Guidelines R 6.4 System Memory Decoupling Guidelines A minimum of eight 0.1 µF low-ESL ceramic capacitors (e.g., 0603 body type, X7R dielectric) are required and must be as close as possible to the GMCH. They should be placed within at most 70 mils to the edge of the GMCH package edge for VSUS_3.3 decoupling, and they should be evenly distributed around the system memory interface signal field including the side of the GMCH where the system memory interface meets the host interface.
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System Memory Design Guidelines R ® Figure 40. Intel 815 Chipset Platform Decoupling Example Yellow lines in Figure 40 show layer-two plane splits. (Printed versions of this document will show the layer two plane splits in the left-side, bottom, right-side, and upper-right-side quadrants enclosed in gray lines.) Note that the layer 1 shapes do NOT cross the plane splits. The bottom shape is a VSS fill over VddSDRAM. The left-side shape is a VSS fill over VddAGP.
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System Memory Design Guidelines R ® Figure 41. Intel 815 Chipset Platform Decoupling Example 6.5 Compensation A system memory compensation resistor (SRCOMP) is used by the GMCH to adjust the buffer characteristics to specific board and operating environment characteristics. Refer to the Intel® 815 Chipset Family: 82815 Graphics and Memory Controller Hub (GMCH) for use with the Universal Socket 370 Datasheet for details on compensation.
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AGP/Display Cache Design Guidelines R 7 AGP/Display Cache Design Guidelines For the detailed AGP interface functionality (e.g., protocols, rules, signaling mechanisms) refer to the latest AGP Interface Specification, Revision 2.0, which can be obtained from http://www.agpforum.org. This design guide focuses only on specific Intel 815 chipset platform recommendations and covers both standard add-in card AGP and down AGP solutions. 7.
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AGP/Display Cache Design Guidelines R 7.1.1 Graphics Performance Accelerator (GPA) The GMCH multiplexes the AGP signal interface with the integrated graphics’ display cache interface. As a result, for a universal motherboard that supports both integrated graphics and addin AGP video cards, display cache (for integrated graphics) must be populated on a card in the universal AGP slot. The card is called a Graphics Performance Accelerator (GPA) card.
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AGP/Display Cache Design Guidelines R Figure 42. AGP Left-Handed Retention Mechanism Figure 43. AGP Left-Handed Retention Mechanism Keepout Information Engineering Change Request number 48 (ECR #48) of the AGP specification details the AGP RM, which is recommended for all AGP cards. These are approved changes to the Accelerated Graphics Port (AGP) Interface Specification, Revision 2.0. Intel intends to incorporate the AGP RM changes into later revisions of the AGP Interface Specification.
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AGP/Display Cache Design Guidelines R ECR #48 can be viewed on the Intel Web site at: http://developer.intel.com/technology/agp/ecr.htm More information regarding this component (AGP RM) is available from the following vendors. Resin Color Black Green 7.2 Supplier Part Number “Left Handed” Orientation (Preferred) “Right Handed” Orientation (Alternate) AMP P/N 136427-1 136427-2 Foxconn P/N 006-0002-939 006-0001-939 Foxconn P/N 009-0004-008 009-0003-008 AGP 2.
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AGP/Display Cache Design Guidelines R 7.2.1 AGP Interface Signal Groups The signals on the AGP interface are broken into three groups: 1X timing domain signals, 2X/4X timing domain signals, and miscellaneous signals. Each group has different routing requirements. In addition, within the 2X/4X timing domain signals, there are three sets of signals. All signals in the 2X/4X timing domain must meet minimum and maximum trace length requirements as well as trace width and spacing requirements.
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AGP/Display Cache Design Guidelines R 7.3 Standard AGP Routing Guidelines These routing guidelines cover a standard AGP solution. This utilizes an AGP compliant device on an external add-in card that plugs into a connector on the motherboard. 7.3.1 1X Timing Domain Routing Guidelines 7.3.1.1 Flexible Motherboard Guidelines • The AGP 1X timing domain signals (Table 20) have a maximum trace length of 4 inches for motherboards that support a Graphics Performance Accelerator (GPA) card.
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AGP/Display Cache Design Guidelines R separately. The maximum length allowed for the AGP interface (on AGP-only motherboards) is 7.25 inches. 7.3.2.1 Flexible Motherboard Guidelines • For motherboards that support either an AGP card or a GPA card in the AGP slot, the maximum length of AGP 2X/4X timing domain signals is 4 inches. • 1:3 trace width-to-spacing is required for AGP 2X/4X signal traces. • AGP 2X/4X signals must be matched their associated strobe (as outlined in Table 20), within ±0.5 inch.
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AGP/Display Cache Design Guidelines R 7.3.2.2 AGP-Only Motherboard Guidelines For motherboards that will not support a GPA card populated in the AGP slot, the maximum AGP 2X/4X signal trace length is 7.25 inches. However, there are different guidelines for AGP interfaces shorter than 6 inches (e.g., all AGP 2X/4X signals are less than 6 inches long) and those longer than 6 inches but shorter than the 7.25 inches maximum.
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AGP/Display Cache Design Guidelines R between them. This pair should be separated from the rest of the AGP signals (and all other signals) by at least 20 mils (1:4). The strobe pair must be length-matched to less than ±0.1 inch (i.e., a strobe and its complement must be the same length, within 0.1 inch). 7.3.3 AGP Routing Guideline Considerations and Summary This section applies to all AGP signals in any motherboard support configuration (e.g.
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AGP/Display Cache Design Guidelines R 7.3.4 AGP Clock Routing The maximum total AGP clock skew, between the GMCH and the graphics component, is 1 ns for all data transfer modes. This 1 ns includes skew and jitter that originates on the motherboard, addin card, and clock synthesizer. Clock skew must be evaluated not only at a single threshold voltage, but at all points on the clock edge that fall within the switching range. The 1 ns skew budget is divided such that the motherboard is allotted 0.
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AGP/Display Cache Design Guidelines R Figure 45. AGP Decoupling Capacitor Placement Example AGP_decoupling_cap_placement NOTE: 7.3.6 This figure is for example purposes only. It does not necessarily represent complete and correct routing for this interface.
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AGP/Display Cache Design Guidelines R 7.4 AGP Down Routing Guidelines These routing guidelines cover an AGP down solution. This allows for an AGP compliant device to be implemented directly on the motherboard without the need for a connector or add-in card. 7.4.1 1X AGP Down Option Timing Domain Routing Guidelines Routing guidelines for an AGP device on the motherboard are very similar to those when the device is implemented with an AGP connector.
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AGP/Display Cache Design Guidelines R Figure 1. AGP Down 2X/4X Routing Recommendations Length: 0.5" - 6.0" Width to spacing: 1:3 Strobe-to-Data Mismatch: ±0.5" Signals AGP Compliant Graphics Device Intel® 82815 Strobes Length: Dependent on Data Width: 5 mil Spacing: 15 mils Strobe-to-Strobe Mismatch: ±0.2" AGP_Down_1x-2x 7.4.
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AGP/Display Cache Design Guidelines R 7.4.4 AGP Clock Routing The maximum total AGP clock skew, between the GMCH and the graphics component, is 1 ns for all data transfer modes. This 1 ns includes skew and jitter that originates on the motherboard and clock synthesizer. Clock skew must be evaluated not only at a single threshold voltage, but at all points on the clock edge that fall within the switching range. For AGP clock routing guidelines for the Intel 815 chipset platform, refer to Section 11.3. 7.
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AGP/Display Cache Design Guidelines R 7.5 AGP 2.0 Power Delivery Guidelines 7.5.1 VDDQ Generation and TYPEDET# AGP specifies two separate power planes: VCC and VDDQ. VCC is the core power for the graphics controller. This voltage is always 3.3V. VDDQ is the interface voltage. In AGP 1.0 implementations, VDDQ was also 3.3V. For the designer developing an AGP 1.0 motherboard, there is no distinction between VCC and VDDQ, as both are tied to the 3.3V power plane on the motherboard. AGP 2.
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AGP/Display Cache Design Guidelines R Figure 46. AGP VDDQ Generation Example Circuit +3.3V +12V C2 U1 1 3 2.2 kΩ C1 1 µF 4 47 µF LT1575 SHDN IPOS VIN INEG 8 5 7 2 R1 VDDQ C3 220 µF R2 6 GND GATE FB COMP 5 10 pF .001 µF C5 C4 R5 7.5 kΩ - 1% 301 - 1% R3 TYPEDET# 1.21 kΩ - 1% R4 AGP_VDDQ_gen_ex_circ The previous figure demonstrates one way to design the VDDQ voltage regulator. This regulator is a linear regulator with an external, low-Rdson FET.
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AGP/Display Cache Design Guidelines R 7.5.2 VREF Generation for AGP 2.0 (2X and 4X) VREF generation for AGP 2.0 is different, depending on the AGP card type used. The 3.3V AGP cards generate VREF locally. That is, they have a resistor divider on the card that divides VDDQ down to VREF (see Figure 47). To account for potential differences between VDDQ and GND at the GMCH and graphics controller, 1.5V cards use source-generated VREF.
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AGP/Display Cache Design Guidelines R Figure 47. AGP 2.0 VREF Generation and Distribution a) 1.5V AGP Card +12V R7 (See note 2) 1 KΩ 1.5V AGP Card R9 300 Ω 1% TYPEDET# VDDQ C8 500 pF R2 200 Ω 1% VrefGC U6 VDDQ REF C9 0.1 uF mosfet VDDQ AGP REF Device GND R6 1 KΩ R5 82 Ω R2 1 KΩ R4 82 Ω GMCH GND C9 500 pF VrefCG Notes: 1. The resistor dividers should be placed near the GMCH. The AGPREF signal must be 5 mils wide and routed 10 mils from adjacent signals. 2.
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AGP/Display Cache Design Guidelines R 7.6 Additional AGP Design Guidelines 7.6.1 Compensation The GMCH AGP interface supports resistive buffer compensation (RCOMP). Tie the GRCOMP pin to a 40 Ω, 2% (or 39 Ω, 1%) pull-down resistor (to ground) via a 10-mil-wide, very short (<0.5 inch) trace. 7.6.2 AGP Pull-Ups AGP control signals require pull-up resistors to VDDQ on the motherboard, to ensure that they contain stable values when no agent is actively driving the bus.
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AGP/Display Cache Design Guidelines R The pull-up/pull-down resistor value requirements are Rmin = 4 kΩ and Rmax = 16 kΩ. The recommended AGP pull-up/pull-down resistor value is 8.2 kΩ. 7.6.2.1 AGP Signal Voltage Tolerance List The following signals on the AGP interface are 3.3V tolerant during 1.
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AGP/Display Cache Design Guidelines R 7.8 AGP / Display Cache Shared Interface As described earlier, the AGP and display cache interfaces of the Intel 815 chipset platform are multiplexed or shared. In other words, the same component pins (balls) are used for both interfaces, although obviously only one interface can be supported at any given time. As a result, almost all display cache interface signals are mapped onto the new AGP interface.
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AGP/Display Cache Design Guidelines R 7.8.2 Display Cache Clocking The display cache is clocked source-synchronously from a clock generated by the GMCH. The display cache clocking scheme uses three clock signals. • LTCLK clocks the SDRAM devices, is muxed with an AGP signal, and should be routed according to the flexible AGP guidelines. • LOCLK and LRCLK clock the input buffers of the universal platform. LOCLK is an output of the GMCH and is a buffered copy of LTCLK.
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Integrated Graphics Display Output R 8 Integrated Graphics Display Output 8.1 Analog RGB/CRT 8.1.1 RAMDAC/Display Interface Figure 49 shows the interface of the RAMDAC analog current outputs with the display. Each DAC output is doubly terminated with a 75 Ω resistance. One 75 Ω resistance is from the DAC output to the board ground and the other termination resistance exists within the display. The equivalent DC resistance at the output of each DAC output is 37.5 Ω.
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Integrated Graphics Display Output R Figure 49. Schematic of RAMDAC Video Interface Display PLL power connects to this segmented power plane Graphics Board Analog power plane Lf 1.8 V Diodes D1, D2: Schottky diodes 1.8 V board power plane 1.8 V board power plane Cf LC filter capacitors, C1, C2: 3.3 pF LC Filter Ferrite bead, FB: 7 Ω @ 100 MHz (Recommended part: Murata BLM11B750S) 1.
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Integrated Graphics Display Output R 8.1.2 Reference Resistor (Rset) Calculation The full-swing video output is designed to be 0.7V according to the VESA video standard. With an equivalent DC resistance of 37.5 Ω (two 75 Ω in parallel; one 75 Ω termination on the board and one 75 Ω termination within the display), the full-scale output current of a RAMDAC channel is 0.7/37.5 Ω = 18.67 mA.
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Integrated Graphics Display Output R Figure 51 shows the recommended RAMDAC component placement and routing. The termination resistance can be placed anywhere along the video route from the RAMDAC output to the VGA connector, as long as the trace impedances are designed as indicated in the following figure. It is advisable to place the pi-filters in close proximity with the VGA connector, to maximize the EMI filtering effectiveness.
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Integrated Graphics Display Output R Figure 52. Recommended RAMDAC Reference Resistor Placement and Connections Graphics Chip IREF ball/pin Position resistor near IREF pin. No toggling signals should be routed near Rset resistor. Short, wide route connecting resistor to IREF pin Rset Resistor for setting RAMDAC reference current 178 Ω, 1%, 1/16 W, SMT, metal film Large via or multiple vias straight down to ground plane RAMDAC_ref_resistor_place_conn 8.1.
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Integrated Graphics Display Output R 8.2 Digital Video Out The Digital Video Out (DVO) port is a scaleable, low-interface port that ranges from 1.1V to 1.8V. This DVO port interfaces with a discrete TV encoder to enable platform support for TVOut, with a discrete TMDS transmitter to enable platform support for DVI-compliant digital displays, or with an integrated TV encoder and TMDS transmitter.
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Hub Interface R 9 Hub Interface The GMCH ball assignment and the ICH ball assignment have been optimized to simplify hub interface routing. It is recommended that the hub interface signals be routed directly from the GMCH to ICH with all signals referenced to VSS (see Figure 53). Layer transition should be kept to a minimum. If a layer change is required, use only two vias per net and keep all data signals and associated strobe signal on the same layer.
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Hub Interface R 9.1.1 Data Signals Hub interface data signals should be routed with a trace width of 5 mils and a trace spacing of 20 mils. These signals can be routed with a trace width of 5 mils and a trace spacing of 15 mils for navigation around components or mounting holes. To break out of the GMCH and the ICH, the hub interface data signals can be routed with a trace width of 5 mils and a trace spacing of 5 mils.
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Hub Interface R Figure 54. Single-Hub-Interface Reference Divider Circuit 1.85 V 300 Ω GMCH ICH HUBREF HUBREF 0.01 µF 300 Ω 0.01 µF 0.1 µF hub_IF_ref_div_1 Figure 55. Locally Generated Hub Interface Reference Dividers 1.85 V GMCH 1.85 V 300 Ω 300 Ω HUBREF ICH HUBREF 300 Ω 0.01 µF 0.01 µF 300 Ω hub_IF_ref_div_2 9.1.4 Compensation Independent hub interface compensation resistors are used by the GMCH and ICH to adjust buffer characteristics to specific board characteristics.
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I/O Subsystem R 10 I/O Subsystem This chapter provides guidelines for connecting and routing the IDE, AC’97, USB, I/O APIC, SMBus, PCI, LPC/FWH, and RTC subsystems. 10.1 IDE Interface This section contains guidelines for connecting and routing the ICH IDE interface. The ICH has two independent IDE channels. This section provides guidelines for IDE connector cabling and motherboard design, including component and resistor placement and signal termination for both IDE channels.
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I/O Subsystem R Figure 56. IDE Minimum/Maximum Routing and Cable Lengths 8 in. max. 10-18 in. Traces ICH IDE connector 5-12 in. 4-6 in. IDE_routing_cable_len Figure 57.
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I/O Subsystem R 10.2 Cable Detection for Ultra ATA/66 An 80-conductor IDE cable is required for Ultra ATA/66. This cable uses the same 40-pin connector as the old 40-pin IDE cable. The wires in the cable alternate: ground, signal, ground, signal,. . . . All ground wires are tied together on the cable (and they are tied to the ground on the motherboard through the ground pins in the 40-pin connector).
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I/O Subsystem R 10.2.1 Host Side Cable Detection BIOS Detects Cable Type Using GPIOs Host-side detection requires the use of two GPI pins (one per IDE controller). The proper way to connect the PDIAG#/CBLID# signal of the IDE connector to the host is shown in Figure 58. All Ultra ATA/66 devices have a 10 kΩ pull-up resistor to 5V. Most GPIO pins on the ICH and all GPIs on the FWH are not 5V tolerant. This requires a resistor divider so that 5V will not be driven to the ICH or FWH pins.
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I/O Subsystem R 10.2.2 Device Side Cable Detection BIOS Queries IDE Device for Cable Type Device-side detection requires only a 0.047 µF capacitor on the motherboard, as shown in Figure 59. This mechanism creates a resistor-capacitor (RC) time constant. The ATA mode 3 or 4 device will drive PDIAG#/CBLID# low and then release it (pulled up through a 10 kΩ resistor). The device will sample the PDIAG# signal after releasing it.
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I/O Subsystem R 10.2.3 Primary IDE Connector Requirements Figure 60. Resistor Schematic for Primary IDE Connectors 22 - 47 Ω PCIRST_BUF#* PDD[15:8] Reset# PDD[7] PDD[6:0] PDA[2:0] PDCS1# PDCS3# PDIOR# PDDREQ 5V 5V 10 kΩ 5.6 kΩ 1 kΩ Primary IDE connector PDIOW# 8.2 kΩ PIORDY IRQ14 PDDACK# 470 Ω CSEL N.C. Pin 32 ICH *Due to ringing, PCIRST# must be buffered.
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I/O Subsystem R 10.2.4 Secondary IDE Connector Requirements Figure 61. Resistor Schematic for Secondary IDE Connectors 22 - 47 Ω Reset# PCIRST_BUF#* SDD[15:8] SDD[7] SDD[6:0] SDA[2:0] SDCS1# SDCS3# SDIOR# 5V 1 kΩ Secondary IDE connector SDIOW# SDDREQ 5V 8.2 kΩ 5.6 kΩ 10 kΩ SIORDY IRQ15 SDDACK# 470 Ω N.C. CSEL Pin 32 ICH * Due to high loading, PCIRST# must be buffered.
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I/O Subsystem R 10.2.5 Layout for Both Host-Side and Device-Side Cable Detection The Intel 815 chipset platform (using the ICH) can use two methods to detect the cable type. Each mode requires a different motherboard layout. It is possible to lay out for both host-side and device-side cable detection and decide the method to be used during assembly. Figure 62 shows the layout that allows for both host-side and drive-side detection. For Host-Side Detection: • R1 is a 0 Ω resistor. • R2 is a 15 kΩ resistor.
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I/O Subsystem R 10.3 AC’97 The ICH implements an AC’97 2.1-compliant digital controller. Any codec attached to the ICH AC-link must be AC’97 2.1 compliant as well. Contact your codec IHV for information on 2.1compliant products. The AC’97 2.1 specification is available on the Intel website: http://developer.intel.com/pc-supp/platform/ac97/index.htm The ICH supports the codec combinations listed in Table 27. Table 27.
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I/O Subsystem R The basic recommendations are as follows: • Special consideration must be given for the ground return paths for the analog signals. • Digital signals routed in the vicinity of the analog audio signals must not cross the power plane split lines. Analog and digital signals should be located as far as possible from each other. • Partition the board with all analog components grouped together in one area and all digital components in another.
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I/O Subsystem R 10.3.2 AC’97 Signal Quality Requirements In a lightly loaded system (e.g., single codec down), AC’97 signal integrity should be evaluated to confirm that the signal quality on the link is acceptable to the codec used in the design. A series resistor at the driver and a capacitor at the codec can be implemented to compensate for any signal integrity issues. The values used will be design dependent and should be verified for correct timings.
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I/O Subsystem R 10.4 Using Native USB Interface The following are general guidelines for the native USB interface: • Unused USB ports should be terminated with 15 kΩ pull-down resistors on both P+/P- data lines. • 15 Ω series resistors should be placed as close as possible to the ICH (<1 inch). These series resistors provide source termination of the reflected signal.
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I/O Subsystem R Figure 63. Recommended USB Schematic Motherboard trace < 1" P+ 15 Ω 45 Ω 47 pF Motherboard trace Driver < 1" P- 15 kΩ 15 Ω USB connector Driver 90 Ω 45 Ω 47 pF ICH 15 kΩ Transmission line USB twisted-pair cable USB_schem The recommended USB trace characteristics are as follows: • Impedance ‘Z0’ = 45.4 Ω • Line delay = 160.2 ps • Capacitance = 3.5 pF • Inductance = 7.3 nH • Res at 20 °C = 53.9 mΩ 10.
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I/O Subsystem R 10.6 SMBus The Alert on LAN signals can be used as: • Alert on LAN signals: 4.7 kΩ pull-up resistors to 3.3VSB are required. • GPIOs: Pull-up resistors to 3.3VSB and the signals must be allowed to change states on power-up. (For example, on power-up the ICH drives heartbeat messages until the BIOS programs these signals as GPIOs.) The values of the pull-up resistors depend on the loading on the GPIO signal. • Not Used: 4.7 kΩ pull-up resistors to 3.3VSB are required.
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I/O Subsystem R 10.8 LPC/FWH 10.8.1 In-Circuit FWH Programming All cycles destined for the FWH will appear on the PCI. The ICH hub interface to the PCI bridge puts all processor boot cycles out on the PCI (before sending them out on the FWH interface). If the ICH is set for subtractive decode, these boot cycles can be accepted by a positive decode agent on PCI. This enables booting from a PCI card that positively decodes these memory cycles.
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I/O Subsystem R 10.9.1 RTC Crystal The ICH RTC module requires an external oscillating source of 32.768 kHz connected on the RTCX1 and RTCX2 pins. Figure 65. External Circuitry of RTC Oscillator 3.3 V VCCSUS VCCRTC2 1 kΩ 1 µF RTCX23 Vbatt 1 kΩ 32768 Hz Xtal R1 10 MΩ RTCX14 C1 0.047 µF C3 18 pF 1 R2 10 MΩ VBIAS5 1 C2 18 pF VSSRTC6 RTC_osc_circ NOTES: 1. The exact capacitor value should be based on the crystal vendor’s recommendations. 2. VCCRTC: Power for RTC well 3.
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I/O Subsystem R 10.9.3 RTC Layout Considerations • Keep the RTC lead lengths as short as possible. Approximately 0.25 inch is sufficient. • Minimize the capacitance between Xin and Xout in the routing. • Put a ground plane under the XTAL components. • Do not route any switching signals under the external components (unless on the other side of the board). • The oscillator VCC should be clean. Use a filter, such as an RC low-pass or a ferrite inductor. 10.9.
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I/O Subsystem R 10.9.5 RTC External RTCRESET Circuit The ICH RTC requires some additional external circuitry. The RTCRESET (RTC Well Test) signal is used to reset the RTC well. The external capacitor (2.2 µF) and the external resistor (8.2 kΩ) between RTCRESET and the RTC battery (Vbat) were selected to create a RC time delay, such that RTCRESET will go high some time after the battery voltage is valid. The RC time delay should be within the range 10–20 ms.
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I/O Subsystem R 10.9.7 RTC Routing Guidelines • All RTC OSC signals (RTCX1, RTCX2, VBIAS) should be routed with trace lengths shorter than 1 inch. The shorter, the better. • Minimize the capacitance between RTCX1 and RTCX2 in the routing (optimally, there would be a ground line between them). • Put a ground plane under all of the external RTC circuitry. • Do not route any switching signals under the external components (unless on the other side of the ground plane). 10.9.
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Clocking R 11 Clocking For an Intel 815 chipset platform, there are two clock specifications. One is for a 2-DIMM solution, and the other is for a 3-DIMM solution. In both specifications only single-ended clocking is supported. Intel 815 chipset platforms using a future 0.13 micron socket 370 processors cannot implement differential clocking. 11.1 2-DIMM Clocking Table 28 shows the characteristics of the clock generator for a 2-DIMM solution. ® Table 28.
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Clocking R Figure 68. Platform Clock Architecture (2 DIMMs) ITP 2.5 V CPU 2_ITP APIC 0 CPU 1 CPU 0 Processor 52 55 50 49 AGP Clock Synthesizer PW RDW N# SEL1 SEL0 SData SClk SDRAM(0) SDRAM(1) SDRAM(2) SDRAM(3) SDRAM(4) SDRAM(5) SDRAM(6) SDRAM(7) DCLK Host unit 32 29 28 30 31 Data 46 45 43 42 M ain Mem ory 2 DIM Ms Address Graphics GM CH Mem ory unit Control 40 39 37 36 34 Hub I/F 3.3 V 3V66 0 DOT 7 Dot clock 26 14.
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Clocking R 11.2 3-DIMM Clocking Table 29 shows the characteristics of the clock generator for a 3-DIMM solution. ® Table 29. Intel CK-815 (3-DIMM) Clocks Number Clock Frequency 2 processor clocks 66/100/133 MHz 13 SDRAM clocks 100 MHz 2 PCI clocks 33 MHz 1 APIC clocks 33 MHz 2 48 MHz clocks 48 MHz 3 3V, 66 MHz clocks 66 MHz 1 REF clock 14.
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Clocking R Figure 69. Universal Platform Clock Architecture (3 DIMMs) Processor APIC CPU 1 CPU 0 2.5 V 1 53 54 CK 815 3D Host I/F 3V66 AGP 12 SDRAM(0) SDRAM(1) SDRAM(2) SDRAM(3) 51 50 47 46 SDRAM(4) SDRAM(5) SDRAM(6) SDRAM(7) 45 42 41 38 SDRAM(8) SDRAM(9) SDRAM(10) SDRAM(11) 37 36 33 32 SDRAM(12) 29 3V66 0 3V66 1 DOT USB REF 0 14.
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Clocking R 11.3 Clock Routing Guidelines This section presents the generic clock routing guidelines for both 2-DIMM and 3-DIMM boards. For 3-DIMM boards, additional analysis must be performed by the motherboard designer to ensure that the clocks generated by the external PCI clock buffer meet the PCI specifications for clock skew at the receiver, when compared with the PCI clock at the ICH. Figure 70.
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Clocking R Table 30. Simulated Clock Routing Solution Space Destination SDRAM MCLK GMCH SCLK 3 Processor BCLK Topology from Previous Figure Section 0 Length Section 1 Length Section 2 Length Section 3 Length Layout 5 N/A < 0.5” A1 N/A Layout 2 N/A < 0.5”=L1 A + 3.5” – L1 0.5” Layout 3 < 0.1” < 0.5” A + 5.2” A + 8” GMCH HCLK <0.5” GMCH HUBCLK Layout 4 N/A <0.5” A + 8” N/A ICH HUBCLK Layout 4 N/A <0.5” A + 8” N/A ICH PCICLK Layout 4 N/A <0.
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Clocking R 11.4 Clock Decoupling Several general layout guidelines should be followed when laying out the power planes for the Intel CK-815 clock generator. • Isolate the power plane to each clock group. • Place local decoupling as close as possible to power pins and connect with short, wide traces and copper. • Connect pins to the appropriate power plane with power vias (larger than signal vias). • Bulk decoupling should be connected to plane with 2 or more power vias.
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Clocking R 11.6 Clock Skew Assumptions The clock skew assumptions in the following table are used in the system clock simulations. Table 31.
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Clocking R 11.7 Intel® CK-815 Power Gating On Wake Events For systems providing functionality with future 0.13 micron socket 370 processors, special handling of wake events is required. When a wake event is triggered, the GMCH and the Intel CK815 must not sample BSEL[1:0] until the signal VTTPWRGD is asserted. This is handled by setting up the following sequence of events: 1. Power is not connected to the Intel CK-815-compliant clock driver until VTTPWRGD12 is asserted. 2.
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Power Delivery R 12 Power Delivery This chapter contains power delivery guidelines. Table 32 provides definitions fro power delivery terms used in this chapter. Table 32. Power Delivery Terminology Term Description Suspend-To-RAM (STR) In the STR state, the system state is stored in main memory and all unnecessary system logic is turned off. Only main memory and logic required to wake the system remain powered.
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Power Delivery R supplied by the power supply. Due to the requirements of main memory and the PCI 3.3 Vaux (and possibly other devices in the system), it is necessary to create a dual power rail. The solutions in this Design Guide are only examples. Many power distribution methods achieve the similar results. When deviating from these examples, it is critical to consider the effect of a change. Figure 71. Power Delivery Map Intel® 815 Chipset Platform Power Map Processor 5V ± 5% 3.
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Power Delivery R 5V Dual Switch This switch will power the 5V Dual plane from the 5V core ATX supply during full-power operation. During Suspend-to-RAM, the 5V Dual plane will be powered from the 5V Standby power supply. Note: The voltage on the 5V Dual plane is not 5V! There is a resistive drop through the 5V Dual Switch that must be considered. Therefore, NO COMPONENTS should be connected directly to the 5V Dual plane.
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Power Delivery R Refer to Section 12.4.1 for more information on the power ramp sequence requirement between 3.3V and 1.85V. System designers need to be aware of this requirement while designing the voltage regulators and selecting the power supply. For further details on the voltage sequencing requirements, refer to the Intel® 815 Chipset Family: 82815 Graphics and Memory Controller Hub (GMCH) For Use With Universal Socket 370 Datasheet.
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Power Delivery R A simplistic DC calculation for a pull-up value is: RMAX = (VCCPU MIN - VIH MIN) / ILEAKAGE MAX RMIN = (VCCPU MAX - VIL MAX) / IOL MAX Since ILEAKAGE MAX is normally very small, RMAX may not be meaningful. RMAX also is determined by the maximum allowable rise time.
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Power Delivery R 12.3 Power Management Signals • A power button is required by the ACPI specification. • PWRBTN# is connected to the front panel on/off power button. The ICH integrates 16 ms debouncing logic on this pin. • AC power loss circuitry has been integrated into the ICH to detect power failure. • It is recommended that the ATXPWROK signal from the power supply connector be routed through a Schmitt trigger to square-off and maintain its signal integrity.
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Power Delivery R 12.3.1 Power Button Implementation The following items should be considered when implementing a power management model for a desktop system. The power states are as follows: S1 – Stop Grant – (processor context not lost) S3 - STR (Suspend to RAM) S4 - STD (Suspend to Disk) 1. 2. 3. 4. 5. S5 - Soft-off Wake: Pressing the power button wakes the computer from S1–S5. Sleep: Pressing the power button signals software/firmware in the following manner: a.
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Power Delivery R 12.4 1.85V/3.3V Power Sequencing This section shows the timings among various signals during different power state transitions. Figure 73. G3-S0 Transition Vcc3.3sus t1 RSMRST# t2 t3 SLP_S3# t4 SLP_S5# t5 SUS_STAT# t6 Vcc3.
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Power Delivery R Figure 74. S0-S3-S0 Transition Vcc3.3sus RSMRST# t24 STPCLK# Stop grant cycle t18 t7 CPUSLP# Go_C3 from ICH Ack_C3 from GMCH DRAM DRAM in STR (CKE low) DRAM active DRAM active t19 SUS_STAT# t20 t11 PCIRST# t12 Cycle 1 from GMCH Cycle 1 from ICH t13 Cycle 2 from GMCH Cycle 2 from ICH t17 CPURST# t21 t23 SLP_S3# SLP_S5# t8 PWROK t22 Vcc3.
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Power Delivery R Figure 75. S0-S5-S0 Transition Vcc3.3sus RSMRST# t24 STPCLK# Stop grant cycle t18 t7 CPUSLP# Go_C3 from ICH Ack_C3 from GMCH DRAM DRAM in STR (CKE low) DRAM active DRAM active t19 SUS_STAT# t20 t11 PCIRST# t12 Cycle 1 from GMCH Cycle 1 from ICH t13 Cycle 2 from GMCH Cycle 2 from ICH t17 CPURST# t21 t23 SLP_S3# t25 t26 SLP_S5# t8 PWROK t22 Vcc3.
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Power Delivery R Table 33. Power Sequencing Timing Definitions Symbol ® Parameter Min. Max. Units 1 25 ms 50 Ns t1 VccSUS Good to RSMRST# inactive t2 VccSUS Good to SLP_S3#, SLP_S5#, and PCIRST# active t3 RSMRST# inactive to SLP_S3# inactive 1 4 RTC clocks t4 RSMRST# inactive to SLP_S5# inactive 1 4 RTC clocks t5 RSMRST# inactive to SUS_STAT# inactive 1 4 RTC clocks t6 SLP_S3#, SLP_S5#, SUS_STAT# inactive to Vcc3.3core good * * t7 Vcc3.
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Power Delivery R 12.4.1 VDDQ/VCC1_85 Power Sequencing For the consideration of long term component reliability, the following power sequence is strongly recommended while the AGP interface of the GMCH is running at 3.3V. If the AGP interface is running at 1.5V, the following power sequence recommendation is no longer applicable. The power sequence recommendation is: • During the power-up sequence, the 1.85V must ramp up to 1.0V before 3.3V ramps above 2.2V • During the power-down sequence, the 1.
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Power Delivery R output buffers that are normally disabled, and the ICH may unexpectedly drive these signals if the 3.3V supply is active while the 1.85V supply is not. Figure 77 shows an example power-on sequencing circuit that ensures the 2V Rule is obeyed. This circuit uses a NPN (Q2) and PNP (Q1) transistor to ensure the 1.85V supply tracks the 3.3V supply. The NPN transistor controls the current through PNP from the 3.3V supply into the 1.
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Power Delivery R 12.4.3 3.3V/V5REF Sequencing V5REF is the reference voltage for 5V tolerance on inputs to the ICH. V5REF must be powered up before or simultaneously to VCC3_3. It must also power down after or simultaneous to VCC3_3. The rule must be followed to ensure the safety of the ICH. If the rule is violated, internal diodes will attempt to draw power sufficient to damage the diodes from the VCC3_3 rail. Figure 78 shows a sample implementation of how to satisfy the V5REF/3.3V sequencing rule.
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System Design Checklist R 13 System Design Checklist 13.1 Design Review Checklist Introduction This checklist highlights design considerations that should be reviewed prior to manufacturing a motherboard that implements an Intel 815 chipset platform for use with the universal socket 370. This is not a complete list and does not guarantee that a design will function properly.
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System Design Checklist R 13.2.2 CMOS Checklist Checklist Items 13.2.3 IERR# • 150 Ω pull-up resistor to VCCCMOS if tied to custom logic, or leave as No Connect (not used by chipset) PREQ# • 200–300 Ω pull-up resistor to VCCCMOS / Connect to ITP or else leave as No Connect. THERMTRIP# • See Section 5.3.1. A20M#, IGNNE#, INIT#, INTR, NMI, SLP#, SMI#, STPCLK# • 150 Ω pull-up to VCMOS / Connect to ICH FERR# • Requires 150 Ω pull-up to VCCCMOS/Connect to ICH.
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System Design Checklist R Checklist Items Recommendations CLKREF • Connect to divider on VCC2.5 or VCC3.3 to create 1.25V reference with a 4.7 µF decoupling capacitor. Resistor divider must be created from 1% tolerance resistors. Do not use VTT as source voltage for this reference! CPUPRES# • Tie to ground. Leave as No Connect or connect to PWRGOOD logic to gate system from powering on if no processor is present. If used, 1 kΩ to 10 kΩ pull-up resistor to VCCCMOS.
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System Design Checklist R Checklist Items Recommendations NO CONNECTS • The following pins must be left as no-connects: A29, A31, A33, AC37, AJ3, AK24, AK30, AL1, AL11, AM2, AN13, AN23, B36, C29, C31, C33, C35, E21, E29, E31, E35, E37, F10, G33, L33, N33, N35, Q33, Q35, Q37, R2, V4, W35, X2, Y1, Z36. NCHCTRL (N37) • 14 Ω pull-up resistor to VTT. 13.3 GMCH Checklist 13.3.
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System Design Checklist R 13.3.2 Designs That Do Not Use the AGP Port Any external graphics implementation not using the AGP port should terminate the GMCH AGP control and strobe signals in the following way: Table 34.
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System Design Checklist R 13.3.3 System Memory Interface Checklist Checklist Items 13.3.4 SM_CSA#[0:3, SM_CSB#[3:0, SMAA[11:8,3:0], SM_MD[0:63], SM_CKE[0:3], S_DQM[0:7] • Connect from GMCH to DIMM0, DIMM1 SM_MAA[7:4], SM_MAB[7:4]# • Connect from GMCH to DIMM0, DIMM1 through 10 ohm resistors SMAA[12] • Connect GMCH through 10 kΩ resistor to transistor junction as per Chapter 4 for systems supporting the universal PGA370 design. SM_CAS# • Connected to R_REFCLK through 10 kΩ resistor.
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System Design Checklist R 13.4 ICH Checklist 13.4.1 PCI Checklist Checklist Items Recommendations AD[31:0] • AD16,17 pass through 100 Ω resistor. ACK 64# • (5V PCI environment) 2.7 kΩ (approximate) pull-up resistors to VCC5. REQ 64# • (3V PCI environment) 8.2 kΩ (approximate) pull-up resistors to VCC3_3. • Each REQ 64# and ACK 64# requires it’s own pull-up. PTCK • Pull-down through 5.6 kΩ to GND • Connect to PCI Connectors only. PTDI, PTRST#, PTMS • Pull-up through 5.
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System Design Checklist R 13.4.2 USB Checklist Checklist Items USBP0P, USBP0N, USB_D1_N, USB_D1_P Recommendations • Decouple through a 47 pF capacitor to GND • Signal goes through 15 Ω resistor • Pull-down through a 15 kΩ resistor to GND 13.4.3 OC#0 • Connected to AGP/AC97 Circuitry (See Intel CRB Schematic pg. 20) USB_D2_N, USB_D2_P, USB_D3_N, USB_D3_P, USB_D4_N, USB_D4_P, USBP1P, USBP1N, USBP0P, USBP0N • Pull-down through a 15 kΩ resistor to GND D-/D+ data lines • Use 15 Ω series resistors.
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System Design Checklist R 13.4.4 IDE Checklist Checklist Items Recommendations PDCS3#, SDCS3#, PDA[2:0], SDA[2:0], PDD[15:0], SDD[15:0], PDDACK#, SDDACK#, PRIOR#, SDIOR#, PDIOW#, SDIOW# • Connect from ICH to IDE Connectors. No external series termination resistors required on those signals with integrated series resistors. PDD7, SDD7 • Pull-down through a 10 kΩ resistor to GND. PDREQ, SDREQ • Pull-down through a 5.6 kΩ resistor to GND.
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System Design Checklist R Checklist Items Recommendations PDD[15:0], PDIOW#, PDIOR#, PDREQ, PDDACK#, PIORDY, PDA[2:0], PDCS1#, PDCS3#, SDD[15:0], SDIOW#, SDIOR#, SDREQ, SDDACK#, SIORDY, SDA[2:0], SDCS1#, SDCS3#, IRQ14, IRQ15 • No external series termination resistors on those signals with integrated series resistors. PCIRST# • The PCIRST# signal should be buffered to the IDE connectors.
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System Design Checklist R 13.5 LPC Checklist Checklist Items Recommendations RCIN# • Pull-up through 8.2 kΩ resistor to VCC3_3 LPC_PME# • Pull-up through 8.2 kΩ resistor to VCC3_3. Do not connect LPC PME# to PCI PME#. If the design requires the Super I/O to support wake from any suspend state, connect Super I/O LPC_PME# to a resume well GPI on the ICH. LPC_SMI# • Pull-up through 8.2 kΩ resistor to VCC3_3. This signal can be connected to any ICH GPI.
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System Design Checklist R 13.6 System Checklist Checklist Items Recommendations KEYLOCK# • Pull-up through 10 kΩ resistor to VCC3_3 PBTN_IN • Connects to PBSwitch and PBin. PWRLED • Pull-up through a 220 Ω resistor to VCC5 R_IRTX • Signal IRTX after it is pulled down through4.7 kΩ resistor to GND and passes through 82 Ω resistor IRRX • Pull-up to 100 kΩ resistor to VCC3_3 • When signal is input for SI/O Decouple through 470 pF capacitor to GND • Pull-down through 4.
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System Design Checklist R 13.8 Clock Synthesizer Checklist Checklist Items Recommendations REFCLK • Connects to R-RefCLK, USB_CLK, SIO_CLK14, and ICHCLK14.
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System Design Checklist R 13.9 LAN Checklist Checklist Items Recommendations TDP, TDN, RDP, RDN • Pull-down through 50 Ω resistor to GND LANAPWR • Passes through 3 kΩ resistor LANCLKRUN • Pull-down through 62 kΩ resistor LAN_ISOLATE# • Connect to SUS_STAT# and PWROK LAN_TEST • Pull-down through a 4.7 kΩ resistor to GND LAN_XTAL1, LAN_XTAL2 • Signal from 25 MHz oscillator • Decouple through a 22 pF capacitor to GND 13.
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System Design Checklist R 13.10.1 Power Checklist Items Recommendations V_CPU_IO[1:0] • The power pins should be connected to the proper power plane for the processor ‘s CMOS compatibility signals. Use one 0.1 µF decoupling capacitor. VCCRTC • No clear CMOS jumper on VCCRTC. Use a jumper on RTCRST# or a GPI, or use a safemode strapping for Clear CMOS VCC3.3 • Requires six 0.1 µF decoupling capacitors VCCSus3.3 • Requires one 0.1 µF decoupling capacitor. VCC1.85 • Requires two 0.
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System Design Checklist R This page is intentionally left blank.
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Third-Party Vendor Information R 14 Third-Party Vendor Information This design guide has been compiled to give an overview of important design considerations while providing sources for additional information. This chapter includes information regarding various third-party vendors who provide products to support the Intel 815 chipset platform for use with the universal socket 370. The list of vendors can be used as a starting point for the designer.
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Third-Party Vendor Information R TMDS Transmitters • Silicon Images John Nelson (408) 873-3111 • Texas Instrument Greg Davis [gdavis@ti.com] (214) 480-3662 • Chrontel Chi Tai Hong [cthong@chrontel.com] (408) 544-2150 TV Encoders • Chrontel Chi Tai Hong [cthong@chrontel.com] (408)544-2150 • Conexant Eileen Carlson [eileen.carlson@conexant.com] (858) 713-3203 • Focus Bill Schillhammer [billhammer@focusinfo.com] (978) 661-0146 • Philips Marcus Rosin [marcus.rosin@philips.
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Appendix A: Customer Reference Board (CRB) R Appendix A: Customer Reference Board (CRB) This section provides a set of Customer Reference Board (CRB) schematics for the Intel 815 chipset platform for use with the universal socket 370.
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5 4 3 2 1 Intel(R) Pentium(R) III Processor (CPUID = 068xh), Intel(R) Celeron(TM) Processor (CPUID = 068xh), and Future 0.13 Micron Socket 370 Processors With Intel(R) 815 Chipset For Use With Universal Socket 370 UNIPROCESSOR CUSTOMER REFERENCE SCHEMATICS D D REVISION 1.
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5 4 3 2 1 BLOCK DIAGRAM VRM 370-PIN SOCKET PROCESSOR CLOCK D D DATA CTRL ADDR AGTL BUS DATA CTRL ADDR AGP Connector 2 DIMM Modules GMCH Digital Video Out Device C C PCI CNTRL UDMA/66 IDE Secondary PCI ADDR/DATA ICH USB AMR Connector AC'97 LINK LPC BUS B USB PORTS PCI CONN 2 PCI CONN 1 IDE Primary B SIO Audio Codec FirmWare Hub Floppy Game Port Keyboard Serial 1 Parallel Serial 2 Mouse A A Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD REV. 1.
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5 4 3 2 B 6 RS#[2:0] RS#[2:0] RS#2 AK28 RS#1 AH22 RS#0 AH26 370 PIN SOCKET A T34 P34 K34 F34 B34 AH36 B22 V36 R36 H36 D36 D32 AD32 AH24 F14 K32 AA37 Y35 370-Pin Socket Part 1 HA#[31:3] HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31 HA#32 HA#33 HA#34 HA#35 AK8 AH12 AH8 AN9 AL15 AH10 AL9 AH6 AK10 AN5 AL7 AK14 AL5 AN7 AE1 Z6 AG3 AC3 AJ1 AE3 AB6 AB4 AF6 Y3 AA1 AK6 Z4 AA3 AD4 X6 AC
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5 4 3 2 1 370PGA SOCKET, PART 2 1 VCMOS R303 75 1% VCMOS VTT VCMOS CLKREF C13 0.
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5 4 3 2 1 Clock Synthesizer VCC_CLK 2 C155 1 1 L14A 1 D USBV3 C154 2 D 2 0.1uF 2 22uF VCC3_3 VCC_CLK L16A 1 1 0.1uF 2 2 0.001uF C158 PCIV3 C159 VCC_CLK L11A 0.001uF 2 1 1 1 C157 0.1uF 2 2 0.001uF C156 1 1 2 C149 C150 C151 1 C109 1 C108 1 C107 1 MEMV3 XTAL_IN 2 1 C143 13 1 12 2R67_U10D 11 33 1 ICH_CLK14 1 R67 C147 2 14 U10D 13 0.1uF 2 22uF U10D_R293 C146 1 C144 2 R293 1K 1 1 1 VCC3SBY C106 U10D_R292 22uF APICCLK_CPU 2 0.
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5 4 3 2 82815B GMCH, PART 1, 4, AND 5 1 VDDQ HOST INTERFACE, POWER & GND VCC3SBY VCC1_8 VTT 1 VCC1_8A R135 D 2 GTLREF C124 C123 150 1% 0.1UF 2 2 0.1UF VTT 2 2 C122 18pF R345 56 5 GMCHHCLK 9,12,14,15,16,17,18,19,24,29 4 4 4 2 C U6-1 2 1 Place near GMCH 4 HADS# PCIRST# CPURST# HLOCK# DEFER# 4 4 4 4 4 4 4 BNR# BPRI# DBSY# DRDY# HIT# HITM# HTRDY# 3 B VCC1_8 L23 C33 1 C41 1 1 2 22nH 0.3A C40 + 2 0.01UF 2 2 0.
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5 4 3 2 1 82815B GMCH, PART 2 MEMORY INTERFACE D SM_MAA[12:0] 4 3 2 1 5 6 7 8 4 3 2 1 RP44 Place HUBREF generation circuit in the middle of GMCH and ICH.
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5 4 3 2 1 82815B GMCH, PART 3 AGP/DISPLAY CACHE & VIDEO INTERFACE U6-3 R168 2GMCH_AGPREF_CQ 1 C 82 1% 2 2 1K 1% C279 500PF 9 9 9 9 B 9 GCBE#0 GCBE#1 GCBE#2 GCBE#3 9 9 9 9 9 9 9 9 9 GFRAME# GDEVSEL# GIRDY# GTRDY# GSTOP# GPAR GREQ# GGNT# PIPE# 9 9 9 9 9 9 ADSTB0 ADSTB0# ADSTB1 ADSTB1# SBSTB SBSTB# ST[2:0] H23 N21 T25 Y26 GCBE0#/LMA3 GCBE1#/LMD10 GCBE2#/LMD13 GCBE3#/LRAS# ST0 ST1 ST2 9 RBF# 9 WBF# CONN_AGPREF C190 0.
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5 4 3 2 1 AGP CONNECTOR 8 8.2K 8 8 RBF# SBA0 SBA[7:0] SBA2 ST[2:0] 8 SBSTB SBA4 SBA6 VCC3SBY C 8 GAD[31:0] GAD31 GAD29 GAD27 GAD25 VDDQ 8 ADSTB1 GAD23 GAD21 GAD19 GAD17 8 8 GCBE#2 8 GIRDY# GDEVSEL# B GPERR# 8 GSERR# GCBE#1 GAD14 GAD12 GAD10 GAD8 8 ADSTB0 GAD7 GAD5 GAD3 GAD1 8 GMCH_AGPREF VDDQ TYPEDET# 32 AGPUSBN 19 RP50 8.2k 8 7 6 5 12,16,17,29,36 ST1 SBA1 1 2 3 4 GIRDY# 8 GDEVSEL# 8 GPERR# GSERR# PIRQ#A PCIRST# 6,12,14,15,16,17,18,19,24,29 GGNT# 8 RP49 8.
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5 4,7,11 7,11 5,11 MEMCLK[7:0] MEMCLK[7:0] 7,11 SM_MAA[12:0] SM_BS[1:0] SM_MAA[12:0] SM_DQM[7:0] 7,11 7,11 SM_CSA#[3:0] SM_CSB#[3:0] 7,11 SM_WE# 7,11 SM_CAS# 7,11 SM_RAS# 7,11 SM_CKE[3:0] 11,12,13,25,30,36 SMBDATA 11,12,13,25,30,36 SMBCLK 4 SM_BS[1:0] SM_CSA#0 SM_CSA#1 SM_CSB#0 SM_CSB#1 SM_DQM0 SM_DQM1 SM_DQM2 SM_DQM3 SM_DQM4 SM_DQM5 SM_DQM6 SM_DQM7 SM_DQM[7:0] 3 S0# S1# S2# S3# WE# CAS# RAS# DQMB0 DQMB1 DQMB2 DQMB3 DQMB4 DQMB5 DQMB6 DQMB7 SMBDATA SMBCLK 24 25 31 44 48 50 51 61 62 80 108 109
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B 7,10 4,7,10 5 5,10 MEMCLK[7:0] 7,10 SM_MAA[12:0] 7 SM_MAB[7:4]# 7,10 7,10 7,10 7,10 7,10 7,10 10,12,13,25,30,36 10,12,13,25,30,36 4 SM_CSA#[3:0] SM_CSB#[3:0] SM_WE# SM_CAS# SM_RAS# SM_CKE[3:0] SMBDATA SMBCLK SM_BS[1:0] SM_DQM[7:0] 3 SM_CKE2 SM_CKE3 S0# S1# S2# S3# WE# CAS# RAS# DQMB0 DQMB1 DQMB2 DQMB3 DQMB4 DQMB5 DQMB6 DQMB7 SMBDATA SMBCLK 24 25 31 44 48 50 51 61 62 80 108 109 134 135 145 146 164 81 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 WP 147 REGE
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5 4 3 2 1 ICH, PART 1 C_BE#[3:0] 4 4 THERMDN B THERMDP 16,17,29 5 16,17,29,36 16,17,29,36 16,17,29,36 16,17,29,36 16,17,29,36 6,9,14,15,16,17,18,19,24,29 16,17,36 16,17,29 16,17,29,36 9,16,17,29 PCPCI_REQ#A PCPCI_GNT#A REQ#B/GPIO1 GNT#B/GPIO17 PCLK_0/ICH FRAME# DEVSEL# IRDY# TRDY# STOP# PCIRST# PLOCK# PAR SERR# PCI_PME# C14 B3 D9 A2 C4 D5 J5 B9 A9 A1 K1 PCPCI_REQ#A PCPCI_GNT#A REQ#B/GPIO1 GNT#B/GPIO17 N6 P5 P4 R5 REQ#A/GPIO0 GNT#A/GPIO16 REQ#B/GPIO1/REQ5# GNT#B/GPIO17/GNT5# 82815 ICH 2
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5 4 3 2 1 ICH, PART 2 VCCRTC CR10 VCC3SBY VCC3SBY VCC3_3 INTRUDER#/GPIO10 CLK14 CLK48 CLK66 C VBIAS RTCX1 RTCX2 RTCRST# Socketed 2 X2 CR2032 2 10M Y4A C380 2 32.
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5 4 3 2 1 FIRMWARE HUB (FWH) SOCKET NOTE: This is a TSOP Implementation D D VCC3_3 1 C424 C423 0.1UF 2 0.1UF 2 2 40 PIN_TSOP_SKT 0.1UF 2 0.1UF 2 2 C401 C395 0.1UF 0.
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5 4 3 SUPER I/O VCC5 2 1 VCC3_3 R93 8.2k 13,36 LPC_PME# 12,17,36 SERIRQ 5 PCLK_1 22 KDAT 22 KCLK 22 MDAT 22 MCLK 12,36 RCIN# 12,36 A20GATE 2 470PF Decoupling 0.1UF 1 1 C345 C336 0.1UF 2 0.
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5 4 3 PCI CONNECTOR 0 (DEV Ah) 2 1 VCC3SBY VCC12M VCC3_3 VCC5 D VCC5 VCC3_3 17 PTCK PTCK 12,17,36 9,12,17,29,36 17 PIRQ#C PIRQ#A PRSNT#21 PIRQ#C PIRQ#A PRSNT#21 17 PRSNT#22 PRSNT#22 5 PCLK_3 PCLK_3 12,36 12,17,29 PREQ#1 AD[31:0] PREQ#1 AD[31:0] AD31 AD29 C 12,17,29 C_BE#[3:0] C_BE#[3:0] AD27 AD25 C_BE#3 AD23 AD21 AD19 AD17 C_BE#2 12,17,29,36 IRDY# IRDY# 12,17,29,36 DEVSEL# DEVSEL# 12,17,36 17,29 12,17,29,36 PLOCK# PERR# SERR# PLOCK# PERR# SERR# C_BE#1 AD14 B AD12 AD1
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4 3 VCC12M VCC3_3 VCC5 VCC5 13,36 GPIO21 PRSNT#32 GPIO21 For Debug Only 12,15,36 SERIRQ SERIRQ 5 PCLK_4 12,36 12,16,29 PREQ#2 AD[31:0] 1R286 0K 2 R_SERIRQ PCLK_4 PREQ#2 AD[31:0] AD31 AD29 C 12,16,29 C_BE#[3:0] AD27 AD25 C_BE#[3:0] C_BE#3 AD23 AD21 AD19 AD17 C_BE#2 12,16,29,36 IRDY# IRDY# 12,16,29,36 DEVSEL# DEVSEL# 12,16,36 16,29 12,16,29,36 PLOCK# PERR# SERR# PLOCK# PERR# SERR# C_BE#1 AD14 B AD12 AD10 PTRST# PTRST# PTMS PTDI PTMS 16,36 PTDI 16,36 PIRQ#C PIRQ#A PIRQ#C
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5 4 3 2 1 IDE CONNECTORS VCC5 D VCC5 PRIMARY IDE CONNECTOR 13 SDD[15:0] 1 PDD[15:0] R102 R100 1K C PDREQ PDIOW# PDIOR# PIORDY PDDACK# IRQ14 PDREQ PDIOW# PDIOR# PIORDY PDDACK# IRQ14 PDCS#1 IDEACTP# 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 PCIRST_BUF# 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 R182 33 J15 2 R_RSTS# SDD7 SDD6 SDD5 SDD4 SDD3 SDD2 SDD1 SDD0 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 13 13 13 13 13 12,36 PRI_PD1 SDREQ SDIOW# SDIOR# SIORDY SDD
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5 4 VCC3SBY VCC3SBY VCC3_3 VCC3_3 USB HUB 3 2 VCC5DUAL 2 1 1 1 1 Do Not Stuff R214 R181 R228 R188 330K F3 330K 330K 26 AC97_USB- 1 R153 2 0K 26 AC97_USB+ 1 R151 2 0K USB_V5 1 1 R179 1 R187 C294 0K 0K C295 9 AGPUSBN 1 R157 2 0K 9 AGPUSBP 1 R150 2 0K 2 0.1UF 2 2 2 2 Do Not Stuff 470K 68UF OC#0 1 13 D USB_PO_A 2 1 1 1 R180 AC_USB_P L21 NPO 1 2 2 2 2 NPO AGP_OC# AC97_OC# AC_USB_N POLYSWITCH_RUSB250 330K 2.
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5 4 3 2 1 PARALLEL PORT VCC5 D D CR3 1 2 VCC5_DB25_CR 1 R84 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 1N4148 RP40 RP39 RP42 RP46 2.2K 2.2K 2.2K 2.2K 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 2 2.
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5 4 3 2 1 Serial Port and Header VCC12 VCC5 D VCC12- D J7A U5 15 15 15 15 15 15 15 15 20 19 18 17 16 15 14 13 12 11 DCD#0 RXD#0 DSR#0 DTR#0 TXD0 CTS#0 RTS#0 RI#0 VCC RY0 RY1 RY2 DA0 DA1 RY3 DA2 RY4 GND VCC12 RA0 RA1 RA2 DY0 DY1 RA3 DY2 RA4 VCC-12 DB9 1 2 3 4 5 6 7 8 9 10 DCD0_C DSR0_C RXD0_C RTS0_C TXD0_C CTS0_C DTR0_C RI0_C 1 6 2 7 3 8 4 9 5 VCC3SBY 1 2 PLACE CLOSE TO HEADER C118 1 1 1 C C181 100PF 100PF 2 100PF 2 100PF 1 2 2 2 2 C186 3 2 Q16 1 ICHRI#_C 1 2 1 2 R
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5 4 3 Keyboard/Mouse Port D D VCC5 VCC5 R185 0K 0K 2 R177 2 1 Floppy Disk Header 1 1 VCC5DUAL 2 L4 F1 R177_F1 2PS2V5_F 1 1 RP45 2 PS2V5 1 2 3 4 1.25A 8 7 6 5 1K C 8 7 6 5 C 1 RP1 4.7K R131 1K 15 KDAT 1 1 2 L_KCLK 2 L_MDAT 15 1 2 3 4 5 6 L5 KCLK J13 J1 L_KDAT 2 PS2_PD 15 2 1 2 3 4 STACKED PS2 CONNECTOR L3 MDAT 1 15 7 8 9 10 11 12 L6 15 MCLK 1 L_MCLK 2 17 16 15 14 13 PS2GND C2 1 1 0.
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5 4 3 2 1 Game Port D D R218 R229 R217 1K 2 1K 2 1K 2 1K 1 1 1 R230 1K 2 2 1 R225 1K 2 R223 1 1 VCC5 VCC5 J6-1 DB15 C J1BUTTON1 J2BUTTON1 15 JOY1X 15 JOY2X 1 R227 2 47 1 R222 2.2K 2 5% 1 R220 2.2K 2 5% 15 JOY2Y 15 JOY1Y J2BUTTON2 J1BUTTON2 15 MIDI_IN 1 R226 MIDI_OUT_R JOY2Y_R JOY1Y_R MIDI_IN_R 2 47 25V 10% C112 470PF 2 470PF 2 1 1 C80 C68 50V 47PF 50V 47PF 2 50V 47PF 50V 47PF C334 2 25V 10% C67 0.01UF 2 2 0.
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5 4 3 2 1 Digital Video Out Connector (FOR DEBUG PURPOSES ONLY) D D J10 FTD[11:0] FTD7 CVBS 6 8 VCC1_8 SP1 D8 G3 10 12 C260 C261 SP2 SP3 D7 G4 5V1 5V2 C263 C262 1.0UF 14 16 2.2UF 1.0UF 1 SP0 1 G2 VCC3_3 1 D9 VCC5 R145 1.0UF 2 C 2 4 D10 G1 2 FTD8 C 1 FTD9 Y D11 2 FTD10 1 3 G1 5 7 G2 9 11 G3 13 15 G4 17 19 1 FTD11 2 8 C 1K 18 20 FTD4 FTD3 FTD2 B FTD1 FTD0 8 8 8 FTCLK0 FTCLK1 FTBLNK# D5 G7 VDD3 VDD4 34 36 VREF 38 40 D4 G8 PD# RST# 1.
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5 4 3 2 1 VCC5 2 VGA CONNECTOR F2 2.5A D 1K BLM11B750S is rated an 75 Ohms an 100MHz 8 VID_RED 1 2 L18 2 R104 1K 2 R103 2 CRT5V_F 1 1 1 D 1 1 1 L20 R107 C195 C210 VCC5 1 3.3PF 2 3.3PF 2 75 1% J9 QS4_3V 2 2 CR5 1 6 8 7 6 5 RP47 8 VID_GREEN 1 2 R106 C216 5VDDCDA 5VDDCCL 5VHSYNC 5VVSYNC 2 5VDDCDA 1 R105 2 0K C212 4 14 10 15 pin VGA CONNECTOR C250 3.
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5 4 3 2 1 Audio/Modem Riser D D 1 VCC3SBY R206 VCC12 VCC5 VCC12- VCC3SBY VCC3SBY VCC5 4.7K VCC3_3 2 J20 C U10A AC97SPKR 14 27,34 1 27 PRI_DWN_RST# PWR_DWN_U PWR_DWN# 3 2 1 3 7 SN74LVC08A B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 2 JP17 13,27 AC_SDOUT 13 AC_RST# B B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 AUDIO_MUTE# GND[0] (ISOLATED) MONO_OUT/PC_BEEP RESV[1] RESV[2] PRIMARY_DN# -12V GND[1] +12V GND[2] +5VD KEY KEY GND[3] RESV[3] RESV[4] +3.
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5 4 3 AC'97 Audio Codec 2 1 0.1UF C308 0.1UF D 2 C354 0.1UF 2 C358 2 D 1 VCC5_AUDIO 1 VCC3_3 1 VCC3_3 VCC12 VCC5_AUDIO 1 C360 1 2 10UF 0.1UF VCC3_3 0.
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5 4 3 2 Audio Connectors 1 STEREO HP/SPEAKER OUT C226 1 1 D R112 FB6 2HP_OUTA_C1 1 2HP_OUTA_FB 1 100UF 20 R118 FB7 2HP_OUTB_C1 1 2HP_OUTB_FB 1 20 100UF J6-4 2 HP_OUTA_C2 HP30 HP29 HP_OUTB_C2 HP28 HP27 HP26 2 C237 D DB15 AUD_STK 1 MICROPHONE INPUT 100PF 2 1 20K C236 100UF-NPO 2 100UF-NPO 2 MIC_IN_R 1 2 C36 2 FB4 R297 2 1 DB15 AUD_STK VCC5_AUDIO U20 C 27 LNLVL_OUT_R C224 1 2LNLVL_R_C1R111 1UF-TANT 20K 2 27 LNLVL_OUT_L 1 C225 2LNLVL_L_C1R113 1UF-TANT 20K 2 C321 1 2 3
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5 4 LAN 3 2 1 VCC5 VCC3SBY VCC3SBY VCC3SBY 1 VCC3SBY VCC3SBY R149 A10 C9 12,16,17 Place C305/C306 Close to Ball A10 C_BE#[3:0] 12,16,17,36 12,16,17,36 12,16,17,36 12,16,17,36 12,16,17,36 12,16,17 9,12,16,17,36 16,17 12,16,17,36 12,16,17 12,36 12,36 6,9,12,14,15,16,17,18,19,24 5 B 30 FRAME# IRDY# TRDY# DEVSEL# STOP# PAR PIRQ#A PERR# SERR# AD20 PREQ#3 PGNT#3 PCIRST# PCLK_5 C_BE#[3:0] 1R204 100 2 R_LANIDS X1 P11 X2 A3 A7 E1 K3 N6 P2 A11 E12 G5 G6 H5 H6 H7 H8 J5 J6 J7 J8 J9 J10 J11 K4
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5 4 3 2 1 LAN VCC3SBY 1 VCC3SBY 1 R146 TDP R148 1 D R138 29 1 D R147 330 330 330 3 12 4 RDN 11 2 29 Place R294 and R295 near 82559 29 29 21 22 23 24 25 26 27 28 C 29 29 SPEEDLED CASE0 CASE1 CASE2 CASE3 CASE4 CASE5 CASE6 CASE7 NO POP R295 LILED 29 JP14 29 NOTE: Chassis Ground, use plane for this signal JP16 2 JP23_PU NC RDC P20 P19 ACTLED 2 330 2 121 1 R23 2 18 15 20 19 R295 LI_CR JP15 1 9 JP18_PU 10 2 2 1 1 TD+ TDRD+ RD- 1 1 2 TDN RDP JP7_P
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4 3 V3SB VCC 3.3V Standby VOLTAGE SWITCH CR1 NDS356AP 2 2 47UF S S D VCC12 Q1 D VCC5DUAL 1 R176 2 0K NPOP C57 47UF D VCC 3.3VSB REGULATOR 1 C56 VCC5 2 1 1 1 This generates 3.3V Standby Power which is on in S0, S1, S3, S4 & S5. It passes 3.3V from the ATX supply in S0/S1, and 3.3VSB (generated by VR2 below) in S3/S4/S5.
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5 4 3 AGP, VCMOS Voltage Regulator 2 1 VCC3_3 1 VCC12 C322 47UF 1 D D 2 C315 10UF 2 VDDQ NO STUFF R210 C317 1 1 2 220UF R210 2 VR6 C270 1 1 C269 1 1 1 C271 C242 C278 C 1UF-X7R 301-1% 1UF-X7R 1UF-X7R 1UF-X7R 1UF-X7R 2 Q14 R162 2 VR_SDB VDDQ_COMP 2 2 VR_SHUTDOWN Q13 IRL2203NS 2 2.2K 1 3 C267 10PF 2 1 C268 2 1C268_R156 1R156 2 7.5K-1% 0.001UF 2 2 1K 2 VDDQ_G2 1 5.
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5 4 3 2 1 Processor Voltage Regulator VCC5 L9 1 1 C76 C441 D 2 2 2 2 2 C440 3300uF 0.1UF 0.1UF 4.7uF 4.7uF 1 2 C439 1 C115 3300uF 0.1UF 10uF 1 C78 1 1 2 1.7uH 2 C66 VCC12 2 D 1 1 1 C117 10 2 R37 2 C456 R343 1.0UF 2 1k 1 2 1.0UF 1 1 VCC3_3 C27 VRM_PWRGD 35 C442 1 2 C 0.001uF R324 220 1 1 1 Stuff only one C449 820uF C444 820uF C450 820uF C445 1000uF C447 4700pF 2 1 B C443 820uF 1 2 ADP3170 2 R330 2.
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5 4 3 System 2 1 VCC3_3 VCC5 NO STUFF. FOR TEST ONLY 1 R272 1 1M 100K D VCC5 VCC5 VCC3_3 1 1 1 C396 R99 R283 1.0UF 2 R124 NO STUFF. FOR TEST ONLY VCC3_3 2 2 0.1UF D SW2 J18 10K 2 10K 2 2 10K C264 C399 + 2 1 R279 2 0K 2 PWRBTN# 1 13 10UF 16V R280 1 1 VCC3SBY 15 IRRX 15 IRTX 1 R269 VCC3_3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 2 R_IRTX 82 1 R270 2 4.
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5 4 3 2 1 ITP RESET CIRCUIT - FOR DEBUG ONLY VCC3SBY VCC3SBY Power Connector and Reset Control 1 System VCC5SBY R123 243 14 VCC12 VCC5SBY VCC2_5 U10B VCC12R302 R 2 ST23 3 1 R94 R62 SN74LVC08A SN74LVC06A has 5V input tolerance 0K VCC5SBY 4 2 1 U12B VCC3SBY 7 14 14 U12A 5 APOK_ST 1 VCC3SBY DBRST 6 VCC_5- 74LVC14A 330 74LVC14A U7A 2 PWRGOOD 4 1 2 7 1 7 D 4 1 DBRESET# 2 4 VCC5 14 VCC3_3 2 D R344 7 SN74LVC06A SN74LVC06A C 7 SN74LVC06A has 5V input toleran
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5 4 3 2 1 VCC5 RP67 D 17 PERR#_PU 12,16,17,29 SERR# 12,16,17 PLOCK# 12,16,17,29 STOP# 12,16,17,29 DEVSEL# 12,16,17,29 TRDY# 12,16,17,29 IRDY# 12,16,17,29 FRAME# 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 16 13 1 2 3 4 SDONEP2 SBOP2 SMBALERT# 13 LDRQ#1 13 GPIO12 13 GPIO13 8 7 6 5 1 2 3 4 PIRQ#D PIRQ#C PIRQ#B PIRQ#A PREQ#3 PREQ#2 PREQ#1 PREQ#0 1 2 3 4 5 6 7 8 5.
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5 4 3 2 1 370-pin Socket Decoupling D D VCCVID DECOUPLING Place in 370 PGA Socket Cavity 4.7UF 1 C52 C53 4.7UF 2 4.7UF 1 C51 2 4.7UF 1 C50 4.7UF 2 1 C49 2 4.7UF 2 C91 4.7UF 1 1 1 C48 4.7UF 2 2 2 C86 4.7UF 2 C55 4.7UF 2 C89 4.7UF 1 1 1 C37 4.7UF 2 C35 4.7UF 1 1 1 C39 4.7UF 2 2 2 C44 4.7UF 2 C88 4.7UF 2 C82 1 1 1 VCCVID C C VTT DECOUPLING B B 0603 Package placed within 200mils of VTT Termination R-packs.
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5 4 GMCH DECOUPLING 3 DISPLAY CACHE DECOUPLING VCC1_8 VDDQ 2 1 ICH DECOUPLING VCC3_3 Display Cache: Near the power pins. Distribute near the 1.8V power pins of the ICH ICH 3.3V Plane Decoupling: Place 1 .uF/.01uF pair in each corner, and 2 on opposite sides close to component if they fit. Distribute near the VCCSUS power pins of the ICH VCC1_8 VCC3SBY 1 1 2 1 1 2 2 1 2 1 2 2 2 2 2 1 2.2UF 2.2UF 0.1UF 0.1UF 0.1UF 0.1UF 1 0.1UF 0.1UF 0.1UF 0.
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5 4 3 2 1 Hub Interface Connector D D J29 5 HUBPRB_3V66 8,12 HL[10:0] HL0 HL1 HL2 C HL3 HL9 8,12 8,12 HLSTB HLSTB# HL10 HL8 HL4 HL5 HL6 HL7 PROBE_CONNECTOR 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 HUBREF 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 7,8,12 C VCC1_8 P08-050-SL-A-G B B A A Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD REV. 1.
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5 4 3 2 1 D D V1_8SB VCC1_8 V3SB R349 R350 R351 1K 1K 22K PWRBTN# 13,34 R352 C 1K C Q30 NPN R353 Q31 NPN 4 THERMTRIP# 1.6K B B Title: INTEL(R) 82815 CHIPSET CUSTOMER REFERENCE BOARD REV. A A THERMTRIP intel 5 4 3 R 1.