Microprocessor User's Manual

3-9
BUS INTERFACE UNIT
The address/status phase starts just before T1 and continues through T1. The data phase starts at
T2 and continues through T4. Figure 3-9 illustrates the T-state relationship of the two phases.
Figure 3-8. BIU State Diagram
Bus Ready
Request Pending
HOLD Deasserted
Bus Not
Ready
Halt Bus Cycle
Bus Ready
No Request Pending
HOLD Deasserted
HOLD Asserted
Request Pending
HOLD Deasserted
T2T1 T3
T4
TI
RES#
Asserted
A1533-02