MATH COPROCESSING
11-12
Figure 11-3. 80C187 Configuration with a Partially Buffered Bus
ALE
PEREQ
RESET
PEREQ
EN
80C187
CKM
NPS2
80C186
Modular
Core
Latch
D15:0
External
Oscillator
CLKOUT
RESET
WR
RD
CLK
NPRD
BUSY
BUSY
ERROR
TOE
D15:8
TOE
Buffer
Buffer
A15:0
D7:0
ERROR
1
NPS1
NPWR
NCS
CS
DEN
DT/R
A1
A2
CMD0
CMD1
AD15:0
2
A1530-0A
