80C186XL/80C188XL Microprocessor User’s Manual
80C186XL/80C188XL Microprocessor User’s Manual 1995
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CONTENTS CHAPTER 1 INTRODUCTION 1.1 HOW TO USE THIS MANUAL....................................................................................... 1-2 1.2 RELATED DOCUMENTS .............................................................................................. 1-3 1.3 ELECTRONIC SUPPORT SYSTEMS ........................................................................... 1-4 1.3.1 FaxBack Service .......................................................................................................
CONTENTS 2.3 INTERRUPTS AND EXCEPTION HANDLING ............................................................ 2-39 2.3.1 Interrupt/Exception Processing ...............................................................................2-39 2.3.1.1 Non-Maskable Interrupts ...............................................................................2-42 2.3.1.2 Maskable Interrupts .......................................................................................2-43 2.3.1.3 Exceptions ......................
CONTENTS CHAPTER 4 PERIPHERAL CONTROL BLOCK 4.1 PERIPHERAL CONTROL REGISTERS........................................................................ 4-1 4.2 PCB RELOCATION REGISTER.................................................................................... 4-1 4.3 RESERVED LOCATIONS ............................................................................................. 4-4 4.4 ACCESSING THE PERIPHERAL CONTROL BLOCK .................................................. 4-4 4.4.1 Bus Cycles ......
CONTENTS 6.4.5 Memory or I/O Bus Cycle Decoding ........................................................................6-17 6.4.6 Programming Considerations ..................................................................................6-17 6.5 CHIP-SELECTS AND BUS HOLD............................................................................... 6-18 6.6 EXAMPLES ................................................................................................................. 6-18 6.6.
CONTENTS 8.4 PROGRAMMING THE INTERRUPT CONTROL UNIT ............................................... 8-11 8.4.1 Interrupt Control Registers ......................................................................................8-12 8.4.2 Interrupt Request Register ......................................................................................8-16 8.4.3 Interrupt Mask Register ...........................................................................................8-16 8.4.4 Priority Mask Register ..
CONTENTS 10.1.3 DMA Requests ........................................................................................................10-3 10.1.4 External Requests ...................................................................................................10-4 10.1.4.1 Source Synchronization ................................................................................10-5 10.1.4.2 Destination Synchronization ..........................................................................10-5 10.1.
CONTENTS 11.3.1.4 Transcendental Instructions ..........................................................................11-5 11.3.1.5 Constant Instructions .....................................................................................11-6 11.3.1.6 Processor Control Instructions ......................................................................11-6 11.3.2 80C187 Data Types ................................................................................................11-7 11.
CONTENTS FIGURES Figure 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 2-26 2-27 2-28 2-29 2-30 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 x Page Simplified Functional Block Diagram of the 80C186 Family CPU ................................2-2 Physical Address Generation .......................................................................................2-3 General Registers ..........................................
CONTENTS FIGURES Figure 3-15 3-16 3-17 3-18 3-19 3-20 3-21 3-22 3-23 3-24 3-25 3-26 3-27 3-28 3-29 3-30 3-31 3-32 3-33 3-34 3-35 3-36 3-37 4-1 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 Page Generating a Normally Not-Ready Bus Signal ...........................................................3-16 Generating a Normally Ready Bus Signal ..................................................................3-17 Normally Not-Ready System Timing ..............................
CONTENTS FIGURES Figure 6-11 6-12 6-13 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 8-13 8-14 8-15 8-16 8-17 8-18 8-19 8-20 8-21 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 10-1 10-2 xii Page Wait State and Ready Control Functions ...................................................................6-16 Using Chip-Selects During HOLD ..............................................................................6-18 Typical System ...........................................
CONTENTS FIGURES Figure 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 11-1 11-2 11-3 11-4 12-1 A-1 A-2 A-3 A-4 A-5 A-6 B-1 Page Source-Synchronized Transfers .................................................................................10-5 Destination-Synchronized Transfers ..........................................................................10-6 Two-Channel DMA Module ........................................................................................10-9 Examples of DMA Priority.....
CONTENTS TABLES Table 1-1 1-2 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 4-1 5-1 6-1 6-2 6-3 6-4 6-5 6-6 7-1 8-1 8-2 8-3 8-4 8-5 9-1 9-2 11-1 11-2 11-3 11-4 11-5 11-6 11-7 xiv Page Comparison of 80C186 Modular Core Family Products ...............................................1-2 Related Documents and Software................................................................................1-3 Implicit Use of General Registers ........................................
CONTENTS TABLES Table C-1 C-2 C-3 C-4 D-1 D-2 D-3 D-4 D-5 Page Instruction Format Variables........................................................................................ C-1 Instruction Operands ................................................................................................... C-2 Flag Bit Functions........................................................................................................ C-3 Instruction Set ..........................................................
CONTENTS EXAMPLES Example Page 5-1 Initializing the Power Management Unit for Power-Save Mode .................................5-14 6-1 Initializing the Chip-Select Unit...................................................................................6-20 7-1 Initializing the Refresh Control Unit ............................................................................7-11 8-1 Initializing the Interrupt Control Unit for Master Mode ................................................
1 Introduction
CHAPTER 1 INTRODUCTION The 8086 microprocessor was first introduced in 1978 and gained rapid support as the microcomputer engine of choice. There are literally millions of 8086/8088-based systems in the world today. The amount of software written for the 8086/8088 is rivaled by no other architecture. By the early 1980’s, however, it was clear that a replacement for the 8086/8088 was necessary. An 8086/8088 system required dozens of support chips to implement even a moderately complex design.
INTRODUCTION The 80C186 Modular Core family is the direct result of ten years of Intel development. It offers the designer the peace of mind of a well-established architecture with the benefits of state-of-theart technology. Table 1-1.
INTRODUCTION Each chapter covers a specific section of the device, beginning with the CPU core. Each peripheral chapter includes programming examples intended to aid in your understanding of device operation. Please read the comments carefully, as not all of the examples include all the code necessary for a specific application. This user’s guide is a supplement to the device data sheet. Specific timing values are not discussed in this guide.
INTRODUCTION Table 1-2. Related Documents and Software (Continued) Document/Software Title Document Order No. ApBUILDER Software 272216 80C186EA Hypertext Manual 272275 80C186EB Hypertext Manual 272296 80C186EC Hypertext Manual 272298 80C186XL Hypertext Manual 272630 ZCON - Z80 Code Converter Available on BBS 1.3 ELECTRONIC SUPPORT SYSTEMS Intel’s FaxBack* service and application BBS provide up-to-date technical information.
INTRODUCTION The following catalogs and information are available at the time of publication: 1. Solutions OEM subscription form 2. Microcontroller and flash catalog 3. Development tools catalog 4. Systems catalog 5. Multimedia catalog 6. Multibus and iRMX® software catalog and BBS file listings 7. Microprocessor, PCI, and peripheral catalog 8. Quality and reliability and change notification catalog 9. iAL (Intel Architecture Labs) technology catalog 1.3.
INTRODUCTION 1.3.2.1 How to Find ApBUILDER Software and Hypertext Documents on the BBS The latest ApBUILDER files and hypertext manuals and data sheets are available first from the BBS. To access the files, complete these steps: 1. Type F from the BBS Main menu. The BBS displays the Intel Apps Files menu. 2. Type L and press . The BBS displays the list of areas and prompts for the area number. 3. Type 25 and press to select ApBUILDER/Hypertext.
INTRODUCTION 1.5 PRODUCT LITERATURE You can order product literature from the following Intel literature centers. 1-800-468-8118, ext. 283 U.S. and Canada 708-296-9333 U.S. (from overseas) 44(0)1793-431155 Europe (U.K.) 44(0)1793-421333 Germany 44(0)1793-421777 France 81(0)120-47-88-32 Japan (fax only) 1.6 TRAINING CLASSES In the U.S. and Canada, you can register for training classes through the Intel customer training center. Classes are held in the U.S. 1-800-234-8806 U.S.
2 Overview of the 80C186 Family Architecture
CHAPTER 2 OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE The 80C186 Modular Microprocessor Core shares a common base architecture with the 8086, 8088, 80186, 80188, 80286, Intel386™ and Intel486™ processors. The 80C186 Modular Core maintains full object-code compatibility with the 8086/8088 family of 16-bit microprocessors, while adding hardware and software performance enhancements.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Address Bus (20 Bits) General Registers AL AH BL BH CL CH DL DH SP BP SI DI Σ Data Bus (16 Bits) CS DS SS ES IP ALU Data Bus (16 Bits) Internal Communications Registers Temporary Registers Bus Control Logic ALU EU Control System External Bus Instruction Queue 1 2 3 4 5 6 Q Bus (8 Bits) Flags Execution Unit (EU) Bus Interface Unit (BIU) A1012-0A Figure 2-1. Simplified Functional Block Diagram of the 80C186 Family CPU 2.1.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE The Execution Unit does not connect directly to the system bus. It obtains instructions from a queue maintained by the Bus Interface Unit. When an instruction requires access to memory or a peripheral device, the Execution Unit requests the Bus Interface Unit to read and write data. Addresses manipulated by the Execution Unit are 16 bits wide.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE During periods when the Execution Unit is busy executing instructions, the Bus Interface Unit sequentially prefetches instructions from memory. As long as the prefetch queue is partially full, the Execution Unit fetches instructions. 2.1.3 General Registers The 80C186 Modular Core family CPU has eight 16-bit general registers (see Figure 2-3). The general registers are subdivided into two sets of four registers.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE The data registers can be addressed by their upper or lower halves. Each data register can be used interchangeably as a 16-bit register or two 8-bit registers. The pointer registers are always accessed as 16-bit values. The CPU can use data registers without constraint in most arithmetic and logic operations. Arithmetic and logic operations can also use the pointer and index registers.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 15 0 CS Code Segment DS Data Segment SS Stack Segment ES Extra Segment Figure 2-4. Segment Registers 2.1.5 Instruction Pointer The Bus Interface Unit updates the 16-bit Instruction Pointer (IP) register so it contains the offset of the next instruction to be fetched. Programs do not have direct access to the Instruction Pointer, but it can change, be saved or be restored as a result of program execution.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.1.6 Flags The 80C186 Modular Core family has six status flags (see Figure 2-5) that the Execution Unit posts as the result of arithmetic or logical operations. Program branch instructions allow a program to alter its execution depending on conditions flagged by a prior operation.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.1.7 Memory Segmentation Programs for the 80C186 Modular Core family view the 1 Mbyte memory space as a group of user-defined segments. A segment is a logical unit of memory that can be up to 64 Kbytes long. Each segment is composed of contiguous memory locations. Segments are independent and separately addressable. Software assigns every segment a base address (starting location) in memory space. All segments begin on 16-byte memory boundaries.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Register Name: Processor Status Word Register Mnemonic: PSW (FLAGS) Register Function: Posts CPU status information. 15 0 O F D F I F T F S F Z F A F P F C F A1035-0A Bit Mnemonic Bit Name Reset State OF Overflow Flag 0 If OF is set, an arithmetic overflow has occurred. DF Direction Flag 0 If DF is set, string instructions are processed high address to low address. If DF is clear, strings are processed low address to high address.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Fully Overlapped Partly Overlapped Segment D Contiguous Segment A Disjoint Logical Segments Segment C Segment B Segment E Physical Memory 0H 10000H 20000H 30000H A1036-0A Figure 2-6. Segment Locations in Physical Memory The four segment registers point to four “currently addressable” segments (see Figure 2-7). The currently addressable segments provide a work space consisting of 64 Kbytes for code, a 64 Kbytes for stack and 128 Kbytes for data storage.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE FFFFFH A B Data: DS: B Code: CS: E Stack: SS: H Extra: ES: J C D E F G H I J K 0H A1037-0A Figure 2-7. Currently Addressable Segments The segment register is automatically selected according to the rules in Table 2-2. All information in one segment type generally shares the same logical attributes (e.g., code or data). This leads to programs that are shorter, faster and better structured.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2C4H Physical Address 2C3H Segment Base 2C2H Offset (3H) 2C1H 2C0H 2BFH 2BEH 2BDH 2BCH 2BBH Offset (13H) Logical Addresses 2BAH 2B9H 2B8H 2B7H 2B6H 2B5H 2B4H 2B3H 2B2H 2B1H Segment Base 2B0H A1038-0A Figure 2-8.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Table 2-2. Logical Address Sources Type of Memory Reference Default Segment Base Alternate Segment Base Offset Instruction Fetch CS NONE IP Stack Operation SS NONE SP Variable (except following) DS CS, ES, SS Effective Address String Source DS CS, ES, SS SI String Destination ES NONE DI BP Used as Base Register SS CS, DS, ES Effective Address Instructions are always fetched from the current code segment.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Before Relocation After Relocation Code Segment Stack Segment CS SS DS ES CS SS DS ES Code Segment Data Segment Stack Segment Data Segment Extra Segment Extra Segment Free Space A1039-0A Figure 2-9. Dynamic Code Relocation To be dynamically relocatable, a program must not load or alter its segment registers and must not transfer directly to a location outside the current code segment. All program offsets must be relative to the segment registers.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.1.10 Stack Implementation Stacks in the 80C186 Modular Core family reside in memory space. They are located by the Stack Segment register (SS) and the Stack Pointer (SP). A system can have multiple stacks, but only one stack is directly addressable at a time. A stack can be up to 64 Kbytes long, the maximum length of a segment. Growing a stack segment beyond 64 Kbytes overwrites the beginning of the segment.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE POP AX POP BX PUSH AX Existing Stack 12 34 10 50 BB AA 00 11 1062 00 11 1062 00 11 1060 22 33 1060 22 33 1060 22 33 105E 44 55 105E 44 55 105E 44 55 105B 66 77 105B 66 77 105B 66 77 105A 88 99 1058 AA BB TOS Bottom of stack 1062 TOS 105A 88 99 105A 88 99 1058 AA BB 1058 AA BB 1056 34 12 1056 34 12 1054 45 67 1054 45 67 1052 89 AB 1052 89 AB 1050 CD EF 1050 CD EF TOS 01 23 1054
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.2 SOFTWARE OVERVIEW All 80C186 Modular Core family members execute the same instructions. This includes all the 8086/8088 instructions plus several additions and enhancements (see Appendix A, “80C186 Instruction Set Additions and Extensions”). The following sections describe the instructions by category and provide a detailed discussion of the operand addressing modes. Software for 80C186 core family systems need not be written in assembly language.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.2.1.1 Data Transfer Instructions The instruction set contains 14 data transfer instructions. These instructions move single bytes and words between memory and registers. They also move single bytes and words between the AL or AX register and I/O ports. Table 2-3 lists the four types of data transfer instructions and their functions. Table 2-3.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE LAHF S Z U A U P U C SAHF 7 6 5 4 3 2 1 0 PUSHF U U U U O D I T S Z U A U P U C POPF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 U = Undefined; Value is indeterminate O = Overflow Flag D = Direction Flag I = Interrupt Enable Flag T = Trap Flag S = Sign Flag Z = Zero Flag A = Auxiliary Carry Flag P = Parity Flag C = Carry Flag A1014-0A Figure 2-11. Flag Storage Format 2.2.1.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Table 2-5 shows the interpretations of various bit patterns according to number type. Binary numbers can be 8 or 16 bits long. Decimal numbers are stored in bytes, two digits per byte for packed decimal and one digit per byte for unpacked decimal. The processor assumes that the operands in arithmetic instructions contain data that represents valid numbers for that instruction. Invalid data may produce unpredictable results.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Table 2-5. Arithmetic Interpretation of 8-Bit Numbers Hex 2.2.1.3 Bit Pattern Unsigned Binary Signed Binary Unpacked Decimal Packed Decimal 07 00000111 7 +7 7 7 89 10001001 137 –119 invalid 89 C5 11000101 197 –59 invalid invalid Bit Manipulation Instructions There are three groups of instructions for manipulating bits within bytes and words. These three groups are logical, shifts and rotates.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Individual bits in bytes and words can also be rotated. The processor does not discard the bits rotated out of an operand. The bits circle back to the other end of the operand. The number of bits to be rotated is taken from the count operand, which can specify either an immediate value or the CL register. The carry flag can act as an extension of the operand in two of the rotate instructions.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE String instructions automatically update the SI register, the DI register, or both, before processing the next string element. The Direction Flag (DF) determines whether the index registers are autoincremented (DF = 0) or auto-decremented (DF = 1). The processor adjusts the DI, SI, or both registers by one for byte strings or by two for word strings.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Unconditional transfer instructions can transfer control either to a target instruction within the current code segment (intrasegment transfer) or to a different code segment (intersegment transfer). The assembler terms an intrasegment transfer SHORT or NEAR and an intersegment transfer FAR. The transfer is made unconditionally when the instruction is executed. CALL, RET and JMP are all unconditional transfers. CALL is used to transfer the program to a procedure.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Table 2-9.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Iteration control instructions can be used to regulate the repetition of software loops. These instructions use the CX register as a counter. Like the conditional transfers, the iteration control instructions are self-relative and can transfer only to targets that are within –128 to +127 bytes of themselves. They are SHORT transfers. The interrupt instructions allow programs and external hardware devices to activate interrupt service routines.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.2.1.6 Processor Control Instructions Processor control instructions (see Table 2-11) allow programs to control various CPU functions. Seven of these instructions update flags, four of them are used to synchronize the microprocessor with external events, and the remaining instruction causes the CPU to do nothing. Except for flag operations, processor control instructions do not affect the flags. Table 2-11.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Immediate operands are constant data contained in an instruction. Immediate data can be either 8 or 16 bits in length. Immediate operands are available directly from the instruction queue and can be accessed quickly. As with a register operand, no bus cycles need to be run to get an immediate operand. Immediate operands can be only source operands and must have a constant value. 2.2.2.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Single Index Encoded in the Instruction Double Index BX BX SI or or or BP BP DI or + SI EU or DI Explicit in the Instruction + Displacement + Effective Address 0000 CS or SS Assumed Unless Overridden by Prefix 0000 or DS BIU 0000 or + ES 0000 + Physical Addr A1015-0A Figure 2-12. Memory Address Computation The displacement is an 8- or 16-bit number contained in the instruction.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE The BX or BP register can be specified as the base register for an effective address calculation. Similarly, either the SI or the DI register can be specified as the index register. The displacement value is a constant. The contents of the base and index registers can change during execution. This allows one instruction to access different memory locations depending upon the current values in the base or base and index registers.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Opcode Mod R/M BX or BP or SI or DI EA A1017-0A Figure 2-14. Register Indirect Addressing Opcode Mod R/M Displacement BX or BP + EA A1018-0A Figure 2-15. Based Addressing Based addressing provides a simple way to address data structures that may be located in different places in memory (see Figure 2-16). A base register can be pointed at the structure. Elements of the structure can then be addressed by their displacements.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Displacement (Rate) High Address Age Rate + Base Register Status Displacement (Rate) + Vac Sick Dept Div Base Register Employee EA EA Age Status Rate Vac Sick Dept Div Employee Low Address A1019-0A Figure 2-16. Accessing a Structure with Based Addressing With indexed addressing, the effective address is calculated by summing a displacement and the contents of an index register (SI or DI, see Figure 2-17).
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Opcode Mod R/M Displacement SI or DI + EA A1020-0A Figure 2-17. Indexed Addressing High Address Array (8) Displacement Array (7) Displacement + Array (6) + Array (5) Index Register Array (4) Index Register 14 Array (3) 2 Array (2) EA Array (1) EA Array (0) 1 Word Low Address A1021-0A Figure 2-18.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Based index addressing generates an effective address that is the sum of a base register, an index register and a displacement (see Figure 2-19). The two address components can be determined at execution time, making this a very flexible addressing mode. Opcode Mod R/M Displacement BX or BP + SI or DI + EA A1022-0A Figure 2-19.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE High Address Displacement Parm 2 Displacement 6 Parm 1 6 + IP + Old BP Base Register (BP) + Old BX Old AX (BP) Base Register + Array (6) Index Register 12 Array (5) Index Register 12 Array (4) Array (3) EA Array (2) EA Array (1) Array (0) Count Temp Status 1 Word Low Address A1024-0A Figure 2-20.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Opcode SI Source EA DI Destination EA A1025-0A Figure 2-21. String Operand 2.2.2.3 I/O Port Addressing Any memory operand addressing modes can be used to access an I/O port if the port is memorymapped. String instructions can also be used to transfer data to memory-mapped ports with an appropriate hardware interface. Two addressing modes can be used to access ports located in the I/O space (see Figure 2-22).
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.2.2.4 Data Types Used in the 80C186 Modular Core Family The 80C186 Modular Core family supports the data types described in Table 2-12 and illustrated in Figure 2-23. In general, individual data elements must fit within defined segment limits. Table 2-12. Supported Data Types Type Integer Description A signed 8- or 16-bit binary numeric value (signed byte or word). All operations assume a 2’s complement representation.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 7 0 Sign Bit Unsigned Byte MSB +2 24 23 63 48 47 +1 15 0 Magnitude 0 87 0 8 7 0 +3 32 31 +2 16 15 +1 0 0 Magnitude +n 0 7 0 7 BCD Digit n +1 0 0 7 BCD Digit 1 +n 7 +1 16 15 +4 +5 MSB 7 Unsigned Word Magnitude +6 +7 0 MSB MSB Sign Bit Binary Coded Decimal (BCD) 0 8 7 Magnitude +3 31 Sign Bit Signed Quad Word* MSB Magnitude Magnitude 15 14 +1 Signed Word Sign Bit Signed Double Word* 0 7 Signed Byte +1 0
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.3 INTERRUPTS AND EXCEPTION HANDLING Interrupts and exceptions alter program execution in response to an external event or an error condition. An interrupt handles asynchronous external events, for example an NMI. Exceptions result directly from the execution of an instruction, usually an instruction fault. The user can cause a software interrupt by executing an “INTn” instruction.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Memory Address 3FE 3FC 82 80 7E 7C 52 50 4E 4C 4A 48 46 44 42 40 3E 3C 3A 38 36 34 32 30 Table Entry CS IP CS IP CS IP CS IP CS IP CS IP CS IP CS IP CS IP CS IP CS IP CS IP 2 Bytes Vector Definition Memory Address 2E 2C User 2A Available 28 26 Type 32 24 22 Type 31 20 Reserved 1E 1C 1A Type 20 18 16 Type 19 - Timer 2 14 12 Type 18 - Timer 1 10 0E Type 17 - Reserved 0C 0A Type 16 - Numerics 08 06 Type 15 - INT3 04 02 Type 14 - INT2 00 Type 255 Type 13 - IN
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2. The Trap Flag bit and Interrupt Enable bit are cleared in the Processor Status Word. This prevents maskable interrupts or single step exceptions from interrupting the processor during the interrupt service routine. 3. The current CS and IP are pushed onto the stack. 4. The CPU fetches the new CS and IP for the interrupt vector routine from the Interrupt Vector Table and begins executing from that point.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Interrupt Enable Bit Trap Flag 2 Stack 1 PSW 0 0 CS SP Processor Status Word IP 3 Code Segment Register Instruction Pointer 4 CS IP Interrupt Vector Table A1029-0A Figure 2-26. Interrupt Sequence 2.3.1.1 Non-Maskable Interrupts The Non-Maskable Interrupt (NMI) is the highest priority interrupt. It is usually reserved for a catastrophic event such as impending power failure. An NMI cannot be prevented (or masked) by software.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.3.1.2 Maskable Interrupts Maskable interrupts are the most common way to service external hardware interrupts. Software can globally enable or disable maskable interrupts. This is done by setting or clearing the Interrupt Enable bit in the Processor Status Word. The Interrupt Control Unit processes the multiple sources of maskable interrupts and presents them to the core via a single maskable interrupt input.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Breakpoint Interrupt — Type 3 The Breakpoint Interrupt is a single-byte version of the INT instruction. It is commonly used by software debuggers to set breakpoints in RAM. Because the instruction is only one byte long, it can substitute for any instruction. Interrupt on Overflow — Type 4 The Interrupt on Overflow trap occurs if the Overflow Flag (OF) bit is set in the Processor Status Word and the INT0 instruction is executed.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.3.2 Software Interrupts A Software Interrupt is caused by executing an “INTn” instruction. The n parameter corresponds to the specific interrupt type to be executed. The interrupt type can be any number between 0 and 255. If the n parameter corresponds to an interrupt type associated with a hardware interrupt (NMI, Timers), the vectors are fetched and the routine is executed, but the corresponding bits in the Interrupt Status register are not altered.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE 2.3.4 Interrupt Response Time Interrupt response time is the time from the CPU recognizing an interrupt until the first instruction in the service routine is executed. Interrupt response time is less for interrupts or exceptions which supply their own vector type. The maskable interrupt has a longer response time because the vector type must be supplied by the Interrupt Control Unit (see Chapter 8, “Interrupt Control Unit”).
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Only the single step exception can occur concurrently with another exception. At most, two exceptions can occur at the same instruction boundary and one of those exceptions must be the single step. Single step is a special case; it is discussed on page 2-48. Ignoring single step (for now), only one exception can occur at any given instruction boundary. An exception has priority over both NMI and the maskable interrupt.
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Single step priority is a special case. If an interrupt (NMI or maskable) occurs at the same instruction boundary as a single step, the interrupt vector is taken first, then is followed immediately by the single step vector. However, the single step service routine is executed before the interrupt service routine (see Figure 2-29).
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE Interrupt Enable Bit (IE) = 1 Trap Flag (TF) = 1 NMI Divide Timer Interrupt Push PSW, CS, IP Fetch Divide Error Vector Interrupt Enable Bit (IE) = 0 Trap Flag (TF) = 0 Push PSW, CS, IP Interrupt Enable Bit (IE) = 0 Fetch NMI Vector Trap Flag (TF) = 0 Push PSW, CS, IP Interrupt Enable Bit (IE) = 0 Fetch Single Step Vector Trap Flag (TF) = 0 Execute Single Step Service Routine IRET Interrupt Enable Bit (IE) = 0 Trap Flag (TF) = ??? Interrupt Enable Bit (IE) =
3 Bus Interface Unit
CHAPTER 3 BUS INTERFACE UNIT The Bus Interface Unit (BIU) generates bus cycles that prefetch instructions from memory, pass data to and from the execution unit, and pass data to and from the integrated peripheral units. The BIU drives address, data, status and control information to define a bus cycle. The start of a bus cycle presents the address of a memory or I/O location and status information defining the type of bus cycle.
BUS INTERFACE UNIT Physical Implementation of the Address Space for 16-Bit Systems Physical Implementation of the Address Space for 8-Bit Systems A19:0 1 MByte FFFFF FFFFE 512 KBytes FFFFF FFFFD 512 KBytes FFFFE FFFFC 2 1 0 5 3 1 4 2 0 D7:0 A19:1 D15:8 BHE D7:0 A0 A1100-0A Figure 3-1. Physical Data Bus Models Byte transfers to even addresses transfer information over the lower half of the data bus (see Figure 3-2). A0 low enables the lower bank, while BHE high disables the upper bank.
BUS INTERFACE UNIT Even Byte Transfer Y+1 X+1 A19:1 D15:8 Y (X) BHE (High) D7:0 A0 (Low) Odd Byte Transfer Y+1 (X + 1) A19:1 D15:8 Y X BHE (Low) D7:0 A0 (High) A1104-0A Figure 3-2.
BUS INTERFACE UNIT (X) (X + 1) A19:1 D15:8 BHE (Low) D7:0 A0 (Low) A1107-0A Figure 3-3. 16-Bit Data Bus Even Word Transfers During a byte read operation, the BIU floats the entire 16-bit data bus, even though the transfer occurs on only one half of the bus. This action simplifies the decoding requirements for read-only devices (e.g., ROM, EPROM, Flash). During the byte read, an external device can drive both halves of the bus, and the BIU automatically accesses the correct half.
BUS INTERFACE UNIT First Bus Cycle Y X (X + 1) A19:1 D15:8 BHE (Low) D7:0 A0 (High) Second Bus Cycle Y+1 X+1 A19:1 D15:8 (Y) X BHE (High) D7:0 A0 (Low) A1108-0A Figure 3-4. 16-Bit Data Bus Odd Word Transfers 3.2.2 8-Bit Data Bus The memory address space on an 8-bit data bus is physically implemented as one bank of 1 Mbyte (see Figure 3-1 on page 3-2). Address lines A19:0 select a specific byte within the bank.
BUS INTERFACE UNIT For word transfers, the word address defines the first byte transferred. The second byte transfer occurs from the word address plus one. Figure 3-5 illustrates a word transfer on an 8-bit bus interface. First Bus Cycle Second Bus Cycle (X + 1) (X) A19:0 D7:0 A19:0 D7:0 A1109-0A Figure 3-5. 8-Bit Data Bus Word Transfers 3.3 MEMORY AND I/O INTERFACES The CPU can interface with 8- and 16-bit memory and I/O devices.
BUS INTERFACE UNIT 3.3.1 16-Bit Bus Memory and I/O Requirements A 16-bit bus has certain assumptions that must be met to operate properly. Memory used to store instruction operands (i.e., the program) and immediate data must be 16 bits wide. Instruction prefetch bus cycles require that both banks be used. The lower bank contains the even bytes of code and the upper bank contains the odd bytes of code. Memory used to store interrupt vectors and stack data must be 16 bits wide.
BUS INTERFACE UNIT T4 T1 T2 T3 T4 CLKOUT ALE Valid Status S2:0 Address AD15:0 Data RD / WR A1507-0A Figure 3-6. Typical Bus Cycle TN CLKOUT Falling Edge Rising Edge Phase 1 (Low Phase) Phase 2 (High Phase) A1111-0A Figure 3-7. T-State Relation to CLKOUT Figure 3-8 shows the BIU state diagram. Typically a bus cycle consists of four consecutive Tstates labeled T1, T2, T3 and T4. A TI (idle) state occurs when no bus cycle is pending. Multiple T3 states occur to generate wait states.
BUS INTERFACE UNIT The address/status phase starts just before T1 and continues through T1. The data phase starts at T2 and continues through T4. Figure 3-9 illustrates the T-state relationship of the two phases. T4 Bus Ready Request Pending HOLD Deasserted Halt Bus Cycle T1 T2 T3 Bus Not Ready Request Pending HOLD Deasserted TI Bus Ready No Request Pending HOLD Deasserted RES# Asserted HOLD Asserted A1533-02 Figure 3-8.
BUS INTERFACE UNIT T4 or TI T1 T2 T3 or TW T4 or TI CLKOUT Address/ Status Phase Data Phase A1113-0A Figure 3-9. T-State and Bus Phases 3.4.1 Address/Status Phase Figure 3-10 shows signal timing relationships for the address/status phase of a bus cycle. A bus cycle begins with the transition of ALE and S2:0. These signals transition during phase 2 of the T-state just prior to T1. Either T4 or TI precedes T1, depending on the operation of the previous bus cycle (see Figure 3-8 on page 3-9).
BUS INTERFACE UNIT T4 or TI T1 T2 CLKOUT 4 1 ALE 2 3 AD15:0 A19:16 5 6 Valid Address S2:0 Valid BHE Valid NOTES: 1. TCHLH TCHSV : Clock high to ALE high, S2:0 valid. 2. TCLAV : Clock low to address valid, BHE valid. 3. TAVLL : Address valid to ALE low (address setup to ALE). 4. TCHLL : Clock high to ALE low. 5. TCLAZ : Clock low to address invalid (address hold from clock low). 6. TLLAX : ALE low to address invalid (address hold from ALE). A1509-0A Figure 3-10.
BUS INTERFACE UNIT Latched Address Signals Signals From CPU 4 3 A19:16 S2:0 I I STB O O 4 LA19:16 3 LS2:0 OE 8 AD15:8 I STB 8 O LA15:8 OE 8 AD7:0 I ALE STB O 8 LA7:0 OE A1102-0A Figure 3-11. Demultiplexing Address Information Table 3-1.
BUS INTERFACE UNIT 3.4.2 Data Phase Figure 3-12 shows the timing relationships for the data phase of a bus cycle. The only bus cycle type that does not have a data phase is a bus halt. During the data phase, the bus transfers information between the internal units and the memory or peripheral device selected during the address/status phase. Appropriate control signals become active to coordinate the transfer of data. The data phase begins at phase 1 of T2 and continues until phase 2 of T4 or TI.
BUS INTERFACE UNIT T3 or TW T2 T4 or TI CLKOUT 4 2 1 RD/ WR 6 7 AD15:0 Write Valid Write Data 5 3 AD15:0 Read Valid Read Data S2:0 NOTES: 1. TCLRL/CLWL, TCLOV : Clock low to valid RD/WR active, write data valid. 2. TCLSH : Clock low to status inactive. 3. TDVCL : Data input valid to clock low. 4. TCLRH/CLWH : Clock valid to RD/WR inactive. 5. TCLDX : Data input HOLD from clock low. 6. TWHDX : Output data HOLD from WR high. 7. TRHAV : Bus no longer floating from RD high. Figure 3-12.
BUS INTERFACE UNIT T1 T2 T3 TW TW T4 CLKOUT ALE Valid S2:0 Address A19:16 Address AD15:0 Valid Write Data WR READY A1040-0A Figure 3-13. Typical Bus Cycle with Wait States ARDY D CLKOUT Q Rising Edge D Q BUS READY Falling Edge SRDY A1041-0A Figure 3-14.
BUS INTERFACE UNIT A normally not-ready system is one in which ARDY and SRDY remain low at all times except to signal a ready condition. For any bus cycle, only the selected device drives either ready input high to complete the bus cycle. The circuit shown in Figure 3-15 illustrates a simple circuit to generate a normally not-ready signal. Note that if no device is selected the bus remains notready indefinitely.
BUS INTERFACE UNIT Wait State Module CS1 Enable CS2 Out ALE Load CLKOUT Clock READY A1081-0A Figure 3-16. Generating a Normally Ready Bus Signal The ARDY input has two major timing concerns that can affect whether a normally ready or normally not-ready signal may be required. Two latches capture the state of the ARDY input (see Figure 3-14 on page 3-15). The first latch captures ARDY on the phase 2 clock edge. The second latch captures ARDY and the result of first latch on the phase 1 clock edge.
BUS INTERFACE UNIT T2 or T3 or TW T3 or TW T4 CLKOUT 1 2 3 ARDY SRDY In a Normally-Not-Ready system, wait states are inserted until (1 or 2) and 3 are met. 1. TARYCH : ARDY active to clock high (assumes ARDY remains active until 3). 2. TSRYCL : SRDY active to clock low. 3. TCLARX, TCLSRY : ARDY and SRDY hold from clock low. ! Failure to meet SRDY setup and hold can cause a device failure (i.e., the bus hangs or operates inappropriately). A1511-0A Figure 3-17.
BUS INTERFACE UNIT T2 T3 TW T4 CLKOUT 2 1 ARDY In a Normally-Ready system, a wait state will be inserted when 1 & 2 are met. (Assumes SRDY is low.) 1. TARYCH : ARDY low to clock high 2. TARYCHL : Clock high to ARDY high (ARDY inactive hold time) T2 T3 TW T4 CLKOUT 1 2 ARDY SRDY Alternatively, in a Normally-Ready system, a wait state will be inserted when1 & 2 are met for SRDY and ARDY. 1. TARYCL, TSRYCL : ARDY and SRDY low to clock low 2.
BUS INTERFACE UNIT An idle bus state may or may not drive the bus. An idle bus state following a bus read cycle continues to float the bus. An idle bus state following a bus write cycle continues to drive the bus. The BIU drives no control strobes active in an idle state except to indicate the start of another bus cycle. 3.5 BUS CYCLES There are four basic types of bus cycles: read, write, interrupt acknowledge and halt.
BUS INTERFACE UNIT TOE, TACC and TCE define the maximum data access requirements for the memory device. These device parameters must be less than the value calculated in the equation column. An equal to or greater than result indicates that wait states must be inserted into the bus cycle. TDF determines the maximum time the memory device can float its outputs before the next bus cycle begins. A TDF value greater than the equation result indicates a buffer fight.
BUS INTERFACE UNIT 3.5.1.1 Refresh Bus Cycles A refresh bus cycle operates similarly to a normal read bus cycle except for the following: • For a 16-bit data bus, address bit A0 and BHE drive to a 1 (high) and the data value on the bus is ignored. • For an 8-bit data bus, address bit A0 drives to a 1 (high) and RFSH is driven active (low). The data value on the bus is ignored. RFSH has the same bus timing as BHE.
BUS INTERFACE UNIT T1 T2 T3 T4 CLKOUT S2:0 Status Valid ALE A19:16 Address Valid BHE [A15:8] A15:0 [AD7:0] A18:16 = 0, A19=Valid Status Valid Address Valid Data Valid WR DT/R DEN A1047-0A Figure 3-21. Typical Write Bus Cycle Table 3-4. Write Bus Cycle Types Status Bits Bus Cycle Type S2 S1 S0 0 1 0 Write I/O — Initiated by executing IN, OUT, INS, OUTS instructions or by the DMA Unit. A15:0 select the desired I/O port.
BUS INTERFACE UNIT Most memory and peripheral devices latch data on the rising edge of the write strobe. Address, chip-select and data must be valid (set up) prior to the rising edge of WR. TAW, TCW and TDW define the minimum data setup requirements. The value calculated by their respective equations must be greater than the device requirements. To increase the calculated value, insert wait states.
BUS INTERFACE UNIT The minimum device data hold time (from WR high) is defined by TDH. The calculated value must be greater than the minimum device requirements; however, the value can be changed only by decreasing the clock rate. Table 3-5.
BUS INTERFACE UNIT T1 T2 T3 T4 TI TI T1 T2 T3 T4 CLKOUT ALE S2:0 INTA0 INTA1 Note Note AD15:0 [AD7:0] Note LOCK DT/R DEN A19:16 [A15:8] A15:8 are unknown A19:16 are driven low BHE RD, WR NOTE: Vector Type is read from AD7:0 only. INTA occurs during T2 in slave mode. A1048-0A Figure 3-23.
BUS INTERFACE UNIT Figure 3-24 shows a typical 82C59A interface example. Bus ready must be provided to terminate both bus cycles in the interrupt acknowledge sequence. NOTE Due to an internal condition, external ready is ignored if the device is configured in Cascade mode and the Peripheral Control Block (PCB) is located at 0000H in I/O space. In this case, wait states cannot be added to interrupt acknowledge bus cycles.
BUS INTERFACE UNIT 3.5.4 HALT Bus Cycle Suspending the CPU reduces device power consumption and potentially reduces interrupt latency time. The HLT instruction initiates two events: 1. Suspends the Execution Unit. 2. Instructs the BIU to execute a HALT bus cycle. After executing a HALT bus cycle, the BIU suspends operation until one of the following events occurs: • • • • An interrupt is generated. A bus HOLD is generated. A DMA request is generated. A refresh request is generated.
BUS INTERFACE UNIT T1 TI TI CLKOUT ALE S2:0 011 AD15:0 [AD7:0] Note 1 [A15:8] Note 1 A19:16 Note 2 BHE [RFSH = 1] NOTES: 1. The AD15:0 [AD7:0] bus can be floating, driving a previous write data value, or driving the next instruction prefetch address value. For an 8-bit device, A15:8 drives either the previous bus address value or the next instruction prefetch address value. 2.
BUS INTERFACE UNIT 3.5.5 Temporarily Exiting the HALT Bus State A DMA request, refresh request or bus hold request causes the BIU to exit the HALT bus state temporarily. This can occur only when in the Active or Idle power management mode. The BIU returns to the HALT bus state after it completes the desired bus operation. However, the BIU does not execute another bus HALT cycle (i.e., ALE and bus cycle status are not regenerated).
BUS INTERFACE UNIT CLKOUT ALE S2:0 AD15:0 [AD7:0] Addr [A15:8] Note 1 A19:16 Note 1 BHE RFSH Note 2 Address Addr A19 = 1, A18:16 = 0 Note 3 NOTES: 1. Previous bus cycle value. 2. Only occurs for BHE on the first refresh bus cycle after entering HALT. 3. BHE = 1 for 16-bit device, RFSH = 0 for 8-bit device. A1514-0A Figure 3-27.
BUS INTERFACE UNIT T4 T1 T2 T3 T4 T1 T2 T3 TI TI TI TI CLKOUT ALE S2:0 Valid Status AD15:0 [AD7:0] Valid Status Addr [A15:8] Note A19:16 Note BHE [RFSH=1] Note Addr Address Addr 8H Valid Valid Data Address Addr 8H Valid NOTE: Drives previous bus cycle value. A1515-0A Figure 3-28. Returning to HALT After a DMA Bus Cycle 3.5.6 Exiting HALT An NMI or any unmasked INTn interrupt causes the BIU to exit HALT.
BUS INTERFACE UNIT CLKOUT Note 1 NMI/INTx ALE S2:0 Valid AD15:0 [AD7:0] Note 2 Addr [A15:8] Note 2 Address A19:16 Note 2 Addr BHE RFSH Note 2 NOTES: 1. For NMI, delay = 4 1/2 clocks. For INTx, delay = 7 1/2 clocks (min). 2. Previous bus cycle value. A1517-0A Figure 3-29. Exiting HALT 3.6 SYSTEM DESIGN ALTERNATIVES Most system designs require no signals other than those already provided by the BIU.
BUS INTERFACE UNIT 3.6.1 Buffering the Data Bus The BIU generates two control signals, DEN and DT/R, to control bidirectional buffers or transceivers. The timing relationship of DEN and DT/R is shown in Figure 3-30. The following conditions require transceivers: • • • • The capacitive load on the address/data bus gets too large. The current load on the address/data bus exceeds device specifications. Additional VOL and VOH drive is required.
BUS INTERFACE UNIT ALE A19:16 Latch Processor Address Bus AD15:0 Address Transceiver Data Bus Data DEN DT/ R CPU Local Bus Memory or I/O Device CS Buffered Bus A1095-0A Figure 3-31. Buffered AD Bus System In a fully buffered system, DEN directly drives the transceiver output enable. A partially buffered system requires that DEN be qualified with another signal to prevent the transceiver from going active for local bus accesses. Figure 3-32 illustrates how to use chip-selects to qualify DEN.
BUS INTERFACE UNIT AD15:8 8 DEN A OE MCS0 B 8 D15:8 T Buffer AD7:0 8 A OE DT/R Buffered Data Bus B 8 D7:0 T Buffer 8 8 Local Data Bus A1058-0B Figure 3-32. Qualifying DEN with Chip-Selects 3.6.2 Synchronizing Software and Hardware Events The execution sequence of a program and hardware events occurring within a system are often asynchronous to each other.
BUS INTERFACE UNIT The WAIT instruction suspends program execution until one of two events occurs: an interrupt is generated, or the TEST input pin is sampled low. Unlike interrupts, the TEST input pin does not require that program execution be transferred to a new location (i.e., an interrupt routine is not executed). In processing the WAIT instruction, program execution remains suspended as long as TEST remains high (at least until an interrupt occurs).
BUS INTERFACE UNIT In general, prefix bytes (such as LOCK) are considered extensions of the instructions they precede. Interrupts, DMA requests and refresh requests that occur during execution of the prefix are not acknowledged until the instruction following the prefix completes (except for instructions that are servicing interrupts during their execution, such as HALT, WAIT and repeated string primitives).Note that multiple prefix bytes can precede an instruction.
BUS INTERFACE UNIT CLKOUT QS0, QS1 A1059-0A Figure 3-33. Queue Status Timing 3.7 MULTI-MASTER BUS SYSTEM DESIGNS The BIU supports protocols for transferring control of the local bus between itself and other devices capable of acting as bus masters. To support such a protocol, the BIU uses a hold request input (HOLD) and a hold acknowledge output (HLDA) as bus transfer handshake signals.
BUS INTERFACE UNIT CLKOUT 1 HOLD 4 2 HLDA 3 AD15:0 DEN Float A19:16 RD, WR, DT/R, BHE, S2:0 LOCK Float NOTES: 1. THVCL : HOLD input to clock low 2. TCHCZ : Clock high to output float 3. TCLAZ : Clock low to output float 4. TCLHAV : Clock low to HLDA high A1518-0A Figure 3-34. Timing Sequence Entering HOLD Table 3-8. Signal Condition Entering HOLD Signal HOLD Condition A19:16, S2:0, RD, WR, DT/R, BHE (RFSH), LOCK These signals float one-half clock before HLDA is generated (i.e., phase 2).
BUS INTERFACE UNIT The major factors that influence bus latency are listed below (in order from longest delay to shortest delay). 1. Bus Not Ready — As long as the bus remains not ready, a bus hold request cannot be serviced. 2. Locked Bus Cycle — As long as LOCK remains asserted, a bus hold request cannot be serviced. Performing a locked move string operation can take several thousands of clocks. 3.
BUS INTERFACE UNIT CLKOUT 1 3 4 HOLD 2 HLDA 5 AD15:0 DEN A19:16 RD, WR, BHE, S2:0 DT/R, LOCK 5 NOTES: 1. HLDA is deasserted, signaling need to run refresh bus cycle. 2. External bus master terminates use of the bus. 3. HOLD deasserted. 4. Hold may be reasserted after one clock. 5. BIU runs refresh cycle. A1061-0A Figure 3-35. Refresh Request During HOLD The device requesting a bus hold must be able to detect a HLDA pulse that is one clock in duration.
BUS INTERFACE UNIT +5 PRE D Q Latched HLDA HLDA CLR RESET HOLD A1535-0A Figure 3-36. Latching HLDA The removal of HOLD must be detected for at least one clock cycle to allow the BIU to regain the bus and execute a refresh bus cycle. Should HOLD go active before the refresh bus cycle is complete, the BIU will release the bus and generate HLDA. 3.7.2 Exiting HOLD Figure 3-37 shows the timing associated with exiting the bus hold state. Normally a bus operation (e.g.
BUS INTERFACE UNIT CLKOUT 1 2 HOLD 3 4 5 HLDA AD15:0 DEN RD, WR, BHE, DT/R, S2:0, A19:16, LOCK NOTES: 1. THVCL : HOLD recognition setup to clock low 2. : HOLD internally synchronized 3. TCLHAV : Clock low to HLDA low 4. TCHCV : Clock high to signal active (high or low) 5. TCLAV : Clock low to signal active (high or low) A1063-0A Figure 3-37. Exiting HOLD 3.8 BUS CYCLE PRIORITIES The BIU arbitrates requests for bus cycles from the Execution Unit, the integrated peripherals (e.g.
BUS INTERFACE UNIT 6. Internal error (e.g., divide error, overflow) interrupt vectoring sequence. 7. Hardware (e.g., INT0, DMA) interrupt vectoring sequence. 8. 80C187 Math Coprocessor error interrupt vectoring sequence. 9. DMA bus cycles. 10. General instruction execution. This category includes read/write operations following a pipelined effective address calculation, vectoring sequences for software interrupts and numerics code execution.
4 Peripheral Control Block
CHAPTER 4 PERIPHERAL CONTROL BLOCK All integrated peripherals in the 80C186 Modular Core family are controlled by sets of registers within an integrated Peripheral Control Block (PCB). The peripheral control registers are physically located in the peripheral devices they control, but they are addressed as a single block of registers. The Peripheral Control Block encompasses 256 contiguous bytes and can be located on any 256-byte boundary of memory or I/O space.
PERIPHERAL CONTROL BLOCK Register Name: PCB Relocation Register Register Mnemonic: RELREG Register Function: Relocates the PCB within memory or I/O space. 15 E T 0 S L M E M R 1 9 R 1 8 R 1 7 R 1 6 R 1 5 R 1 4 R 1 3 R 1 2 R 1 1 R 1 0 R 9 R 8 A1262-0A Bit Mnemonic Reset State Bit Name Function ET Escape Trap 0 If ET is set, the CPU will trap when an ESC instruction is executed. SL Slave/Master 0 If SL is set, the Interrupt Control Unit operates in slave mode.
PERIPHERAL CONTROL BLOCK Table 4-1.
PERIPHERAL CONTROL BLOCK 4.3 RESERVED LOCATIONS Many locations within the Peripheral Control Block are not assigned to any peripheral. Unused locations are reserved. Reading from these locations yields an undefined result. If reserved registers are written (for example, during a block MOV instruction) they must be set to 0H. NOTE Failure to follow this guideline could result in incompatibilities with future 80C186 Modular Core family products. 4.
PERIPHERAL CONTROL BLOCK 4.4.3 F-Bus Operation The F-Bus functions differently than the external data bus for byte and word accesses. All write transfers on the F-Bus occur as words, regardless of how they are encoded. For example, the instruction OUT DX, AL (DX is even) will write the entire AX register to the Peripheral Control Block register at location [DX]. If DX were an odd location, AL would be placed in [DX] and AH would be placed at [DX–1].
PERIPHERAL CONTROL BLOCK 4.4.3.1 Writing the PCB Relocation Register Whenever mapping the Peripheral Control Block to another location, the user should program the Relocation Register with a byte write (i.e., OUT DX, AL). Internally, the Relocation Register is written with 16 bits of the AX register, while externally the Bus Interface Unit runs a single 8-bit bus cycle. If a word instruction (i.e.
PERIPHERAL CONTROL BLOCK As an example, to relocate the Peripheral Control Block to the memory range 10000-100FFH, the user would program the PCB Relocation Register with the value 1100H. Since the Relocation Register is part of the Peripheral Control Block, it relocates to word 10000H plus its fixed offset. NOTE Due to an internal condition, external ready is ignored if the device is configured in Cascade mode and the Peripheral Control Block (PCB) is located at 0000H in I/O space.
5 Clock Generation and Power Management
CHAPTER 5 CLOCK GENERATION AND POWER MANAGEMENT The clock generation and distribution circuits provide uniform clock signals for the Execution Unit, the Bus Interface Unit and all integrated peripherals. The 80C186 Modular Core Family processors have additional logic that controls the clock signals to provide power management functions. 5.1 CLOCK GENERATION The clock generation circuit (Figure 5-1) includes a crystal oscillator, a divide-by-two counter and power-save and reset circuitry.
CLOCK GENERATION AND POWER MANAGEMENT 5.1.1.1 Oscillator Operation A phase shift oscillator operates through positive feedback, where a non-inverted, amplified version of the input connects back to the input. A 360° phase shift around the loop will sustain the feedback in the oscillator. The on-chip inverter provides a 180° phase shift. The combination of the inverter’s output impedance and the first load capacitor (see Figure 5-2) provides another 90° phase shift.
CLOCK GENERATION AND POWER MANAGEMENT Choose C1 and L1 component values in the third overtone crystal circuit to satisfy the following conditions: • The LC components form an equivalent series resonant circuit at a frequency below the fundamental frequency. This criterion makes the circuit inductive at the fundamental frequency. The inductive circuit cannot make the 90° phase shift and oscillations do not take place.
CLOCK GENERATION AND POWER MANAGEMENT To examine the parallel resonant frequency, refer to Figure 5-3(c), an equivalent circuit to Figure 5-3(b). The capacitance connected to L1 is 200 pF in parallel with 20 pF. The equivalent capacitance is still about 200 pF (within 10%) and the equation in Figure 5-4(a) now yields the parallel resonant frequency.
CLOCK GENERATION AND POWER MANAGEMENT 5.1.1.2 Selecting Crystals When specifying crystals, consider these parameters: • Resonance and Load Capacitance — Crystals carry a parallel or series resonance specification. The two types do not differ in construction, just in test conditions and expected circuit application. Parallel resonant crystals carry a test load specification, with typical load capacitance values of 15, 18 or 22 pF. Series resonant crystals do not carry a load capacitance specification.
CLOCK GENERATION AND POWER MANAGEMENT An important consideration when using crystals is that the oscillator start correctly over the voltage and temperature ranges expected in operation. Observe oscillator startup in the laboratory. Varying the load capacitors (within about ± 50%) can optimize startup characteristics versus stability. In your experiments, consider stray capacitance and scope loading effects.
CLOCK GENERATION AND POWER MANAGEMENT Reset may be either cold (power-up) or warm. Figure 5-6 illustrates a cold reset. Assert the RES input during power supply and oscillator startup. The processor’s pins assume their reset pin states a maximum of 28 X1 periods after X1 and VCC stabilize. Assert RES 4 additional X1 periods after the device pins assume their reset states. Applying RES when the device is running constitutes a warm reset (see Figure 5-7).
CLOCK GENERATION AND POWER MANAGEMENT X1 Vcc Vcc and X1 stable to output valid 28 X1 periods (max) CLKOUT UCS, LCS MCS3:0, NCS TMR OUT0 TMR OUT1 PCS6:0 HLDA, ALE A19:16 AD15:0, S2:0 RD, WR, DEN DT/R, LOCK RES RESET Vcc and X1 stable to RES high, approximately 32 X1 periods. RES high to first bus activity, 7 CLKOUT periods. NOTE: CLKOUT synchronization occurs 1 1/2 X1 periods after RES is sampled low. A1508-0B Figure 5-6.
CLOCK GENERATION AND POWER MANAGEMENT X1 CLKOUT UCS, LCS MCS3:0 PCS6:0,NCS TMR OUT0 TMR OUT1 HLDA, ALE A19/S6: A16 AD15:0 S2:0, RD WR, DEN DT/R LOCK RES RESET Minimum RES low time 4 CLKOUT periods. RES high to first bus activity 7 CLKOUT periods. A1522-0B Figure 5-7. Warm Reset Waveform At the second falling CLKOUT edge after sampling RES inactive, the processor deasserts RESET. Bus activity starts 6½ CLKOUT periods after recognition of RES in the logic high state.
CLOCK GENERATION AND POWER MANAGEMENT X1 RES RESYNC (Internal) 5 2 1 1 CLKOUT 2 3 RESET 6 4 NOTES: 1. Setup of RES to falling X1. 2. RESYNC pulse generated. 3. RESYNC drives CLKOUT high, resynchronizing the clock generator. 4. RESET goes active. 5. RES allowed to go inactive after minimum 4 CLKOUT cycles. 6. RESET goes inactive 1 1/2 CLKOUT cycles after RES sampled inactive. A1523-0A Figure 5-8. Clock Synchronization at Reset 5.
CLOCK GENERATION AND POWER MANAGEMENT 5.2.1 Power-Save Mode Power-Save mode is a means for reducing operating current. Power-Save mode enables a programmable clock divider in the clock generation circuit. NOTE Power-Save mode can be used to stretch bus cycles as an alternative to wait states. Possible clock divisor settings are 1 (undivided), 4, 8 and 16. The divided frequency feeds the core, the integrated peripherals and CLKOUT.
CLOCK GENERATION AND POWER MANAGEMENT Register Name: Power Save Register Register Mnemonic: PWRSAV Register Function: Enables and sets clock division factor. 15 0 P S E N F 1 F 0 A1130-0A Bit Mnemonic Bit Name Reset State Function PSEN Power Save Enable 0H Setting this bit enables Power Save mode and divides the internal operating clock by the value defined by F1:0. Clearing this bit disables Power-Save mode and forces the CPU to operate at full speed.
CLOCK GENERATION AND POWER MANAGEMENT T2 T3 T4 CLKOUT 2 WR 1 NOTES: 1. : Write to Power-Save Register (as viewed on the bus). 2. : Low-going edge of T3 starts new clock rate. A1124-0A Figure 5-10. Power-Save Clock Transition 5.2.1.2 Leaving Power-Save Mode Power-Save mode continues until one of three events occurs: execution clears the PSEN bit in the Power-Save Register, an unmasked interrupt occurs or an NMI occurs.
CLOCK GENERATION AND POWER MANAGEMENT $mod186 name ;FUNCTION: ; ; ; SYNTAX: ; INPUTS: ; ; OUTPUTS: ; NOTE: ; example_PSU_code RFCON PSEN This function reduces CPU power consumption by dividing the CPU operating frequency by a divisor. extern void far power_save(int divisor); divisor - This variable represents F0, F1 and F2 of PWRSAV.
6 Chip-Select Unit
CHAPTER 6 CHIP-SELECT UNIT Every system requires some form of component-selection mechanism to enable the CPU to access a specific memory or peripheral device. The signal that selects the memory or peripheral device is referred to as a chip-select. Besides selecting a specific device, each chip-select can be used to control the number of wait states inserted into the bus cycle. Devices that are too slow to keep up with the maximum bus bandwidth can use wait states to slow the bus down. 6.
CHIP-SELECT UNIT 27C256 74AC138 D7:0 A1:13 A0:12 A19 A3 Y7 Selects 896K to 1M A18 A2 Y6 Selects 768K to 896K A17 A1 Y5 D15:8 RD OE A16 CS (A) Chip-Selects Using Addresses Directly Y4 ALE E1 Y3 HLDA E2 Y2 E3 Y1 Selects 128K to 256K Y0 Selects 0 to 128K (B) Chip-Selects Using Simple Decoder A1168-0A Figure 6-1. Common Chip-Select Generation Methods 6.
CHIP-SELECT UNIT Internal Address Bus = Base = Block Size UCS = Block Size LCS = Block Size/4 MCS3 = Block Size/4 MCS2 = Block Size/4 MCS1 = Block Size/4 MCS0 = Base Memory/ I/O Selector MS Base + 0 PCS0 Base + 128 PCS1 Base + 256 PCS2 Base + 384 PCS3 Base + 512 PCS4 Base + 640 Base + 768 A Internal Address Bit A1 A2 B MUX PCS5 A/B PCS6 EX Control Bit A1139-0A Figure 6-2.
CHIP-SELECT UNIT UCS Mapped only to the upper memory address space; selects the BOOT memory device (EPROM or Flash memory types). LCS Mapped only to the lower memory address space; selects a static memory (SRAM) device that stores the interrupt vector table, local stack, local data, and scratch pad data. MCS3:0 Mapped only to memory address space; selects additional SRAM memory, DRAM memory, or the system bus.
CHIP-SELECT UNIT By combining LCS, UCS and MCS3:0, you can cover up to 786 Kbytes of memory address space. Methods such as those shown in Figure 6-1 on page 6-2 can be used to decode the remaining 256 Kbytes. The PCS6:0 chip-selects access a contiguous, 896-byte block of memory or I/O address space. Each chip-select goes active for one-seventh of the block (128 bytes). The start address is programmed in the PACS register (Figure 6-8 on page 6-10); it can begin on any 1 Kbyte boundary.
CHIP-SELECT UNIT 6.4 PROGRAMMING Four registers determine the operating characteristics of the chip-selects. The Peripheral Control Block defines the location of the Chip-Select Unit registers. Table 6-1 lists the registers and their associated programming names. Table 6-1.
CHIP-SELECT UNIT Register Name: UCS Control Register Register Mnemonic: UMCS Register Function: Controls the operation of the UCS chip-select. 15 0 U 1 7 U 1 5 U 1 6 U 1 3 U 1 4 U 1 2 U 1 1 R 2 U 1 0 R 1 R 0 A1141-0A Bit Mnemonic Bit Name Reset State Function U17:10 Start Address 0FFH Defines the starting address for the chip-select. During memory bus cycles, U17:10 are compared with the A17:10 address bits.
CHIP-SELECT UNIT Register Name: LCS Control Register Register Mnemonic: LMCS Register Function: Controls the operation of the LCS chip-select. 15 0 U 1 7 U 1 5 U 1 6 U 1 3 U 1 4 U 1 2 U 1 1 R 2 U 1 0 R 1 R 0 A1142-0A Bit Mnemonic Bit Name Reset State Function U17:10 Ending Address 00H Defines the ending address for the chip-select. During memory bus cycles, U17:10 are compared with the A17:10 address bits. A less than result enables the LCS chip-select if A19:18 are both zero.
CHIP-SELECT UNIT Register Name: MCS Control Register Register Mnemonic: MMCS Register Function: Controls the operation of the MCS chip-selects. 15 U 1 9 0 U 1 8 U 1 7 U 1 5 U 1 6 U 1 3 U 1 4 R 2 R 1 R 0 A1143-0B Bit Mnemonic Bit Name Reset State Function U19:13 Start Address XXH Defines the starting address for the block of MCS chip-selects. During memory bus cycles, U19:13 are compared with the A19:13 address bits. An equal to or greater than result enables the MCS chip-select.
CHIP-SELECT UNIT Register Name: PCS Control Register Register Mnemonic: PACS Register Function: Controls the operation of the PCS chip-selects. 15 U 1 9 0 U 1 8 U 1 7 U 1 5 U 1 6 U 1 3 U 1 4 R 2 R 1 R 0 A1143-0B Bit Mnemonic Bit Name Reset State Function U19:13 Start Address XXH Defines the starting address for the block of PCS chip-selects. During memory or I/O bus cycles, U19:13 are compared with the A19:13 address bits.
CHIP-SELECT UNIT Register Name: MCS and PCS Alternate Control Register Register Mnemonic: MPCS Register Function: Controls operation of the MCS and PCS chipselects. 15 0 M 6 M 5 M 4 M 3 M 2 M 1 M 0 E X M S R 2 R 1 R 0 A1144-0A Bit Mnemonic Bit Name Reset State Function M6:0 Block Size XXH Defines the block size for the MCS chip-selects. Table 6-5 on page 6-14 lists allowable values. EX Pin Selector XH Setting EX configures PCS6:5 as chip-selects.
CHIP-SELECT UNIT The UMCS and LMCS registers can be programmed in any sequence. To program the MCS and PCS chip-selects, follow this sequence: 1. Program the MPCS register 2. Program the MMCS register to enable the MCS chip-selects. 3. Program the PACS register to enable the PCS chip-selects. 6.4.2 Programming the Active Ranges The active ranges of the chip-selects are determined by a combination of their starting or ending addresses and block sizes.
CHIP-SELECT UNIT 6.4.2.2 LCS Active Range The LCS starting address is fixed at zero in memory address space; its ending address is the programmed block size minus one. Table 6.3 defines the acceptable values for the field (U17:10) in the LMCS register that determines the LCS block size and ending address. Table 6.3 LCS Active Range 6.4.2.
CHIP-SELECT UNIT Table 6-5. MCS Block Size and Start Address Restrictions MPCS Block Size Bits Block Size (Kbytes) MMCS Start Address Restrictions M6 M5 M4 M3 M2 M1 M0 0 0 0 0 0 0 1 8 None 0 0 0 0 0 1 X 16 U13 must be zero. 0 0 0 0 1 X X 32 U14:13 must be zero. 0 0 0 1 X X X 64 U15:13 must be zero. 0 0 1 X X X X 128 U16:13 must be zero. 0 1 X X X X X 256 U17:13 must be zero. 1 X X X X X X 512 U18:13 must be zero.
CHIP-SELECT UNIT 6.4.2.4 PCS Active Range Each PCS chip-select starts at an offset above the base address programmed in the PACS register and is active for 128 bytes. The base address can start on any 1 Kbyte memory or I/O address location. Table 6-6 lists the active range for each PCS chip-select. Table 6-6. PCS Active Range ChipSelect 6.4.
CHIP-SELECT UNIT BUS READY R2 Control Bit READY Wait State Value (R1:0) Wait State Counter Wait State Ready A1137-0A Figure 6-11. Wait State and Ready Control Functions The R2 control bit determines whether the bus cycle completes normally (requires bus ready) or unconditionally (ignores bus ready). The R1:0 bits define the number of wait states to insert into the bus cycle.
CHIP-SELECT UNIT For example, assume MCS3 overlaps UCS. MCS3 is programmed for two wait states and requires bus ready, while UCS is programmed for no wait states and ignores bus ready. An access to the overlapped region has two wait states and requires bus ready (the values programmed in the R2:0 bits in the MPCS register). Be cautious when overlapping chip-selects with different wait state or bus ready programming.
CHIP-SELECT UNIT 6.5 CHIP-SELECTS AND BUS HOLD The Chip-Select Unit decodes only internally generated address and bus state information. An external bus master cannot make use of the Chip-Select Unit. During HLDA, all chip-selects remain inactive. The circuit shown in Figure 6-12 allows an external bus master to access a device during bus HOLD. CSU Chip Select Device select External Master Chip Select A1167-0A Figure 6-12. Using Chip-Selects During HOLD 6.
CHIP-SELECT UNIT Processor ARDY SRDY ALE A19:16 AD15:0 AD Bus L 20 a Addr t Bus c h EPROM 128K D R A M 256K SRAM 32K Floppy Disk Control DACK DRQ A0 CE CE CE CE DRQ PCS1 UCS MCS3:0 4 LCS PCS0 A1138-0A Figure 6-13.
CHIP-SELECT UNIT $ $ TITLE MOD186XREF NAME (Chip-Select Unit Initialization) CSU_EXAMPLE_1 ; External reference from this module $ include(PCBMAP.INC ;File declares register ;locations and names. ; Module equates ; Configuration equates INTRDY EXTRDY IO ALLPCS EQU EQU EQU EQU 0004H 0000H 0080H 0040H ;Internal bus ready modifier ;External bus ready modifier ;PCS Memory/IO select modifier ;PCS/Latched address modifier ;Below is a list of the default system memory and I/O environment.
CHIP-SELECT UNIT DRAM_BASE DRAM_SIZE DRAM_WAIT DRAM_RDY EQU EQU EQU EQU 256 256 0 INTRDY ;window start address in Kbytes ;window size in Kbytes ;wait states ;ignore bus ready ;The MPCS register is used to program both the MCS and PCS chip-selects. ;Below are the equates for the I/O peripherals (also used to program the PACS ;register.
CHIP-SELECT UNIT mov mov out dx, MPCS_REG ax, MPCS_VAL dx, al ;ready for PCS lines 4-6 ;as well as MCS programming mov mov out dx, MMCS_REG ax, MMCS_VAL dx, al ;set up DRAM chip-selects mov mov out dx, PACS_REG ax, PACS_VAL dx, al ;set up I/O chip-select CODE ENDS ; ;Power-on reset code to get started ; ASSUME CS:POWER_ON POWER_ON SEGMENT AT 0FFFFH mov mov out jmp ENDS dx, UMCS_REG ax, UMCS_VAL dx, al FW_START DD 256 DUP (?) ;point to UMCS register ;reprogram UMCS to match system ;requirements
7 Refresh Control Unit
CHAPTER 7 REFRESH CONTROL UNIT The Refresh Control Unit (RCU) simplifies dynamic memory controller design with its integrated address and clock counters. Figure 7-1 shows the relationship between the Bus Interface Unit and the Refresh Control Unit. Integrating the Refresh Control Unit into the processor allows an external DRAM controller to use chip-selects, wait state logic and status lines.
REFRESH CONTROL UNIT 7.1 THE ROLE OF THE REFRESH CONTROL UNIT Like a DMA controller, the Refresh Control Unit runs bus cycles independent of CPU execution. Unlike a DMA controller, however, the Refresh Control Unit does not run bus cycle bursts nor does it transfer data. The DRAM refresh process freshens individual DRAM rows in “dummy read” cycles, while cycling through all necessary addresses. The microprocessor interface to DRAMs is more complicated than other memory interfaces.
REFRESH CONTROL UNIT Refresh Control Unit Operation BIU Refresh Bus Operation Set "E" Bit Refresh Request Acknowledged Execute Memory Read Load Counter From Refresh Clock Interval Register Increment Address Counter = ? Executed Every Clock Remove Request Continue Decrement Counter Generated BIU Request A1265-0A Figure 7-2. Refresh Control Unit Operation Flow Chart The nine-bit refresh clock counter does not wait until the BIU services the refresh request to continue counting.
REFRESH CONTROL UNIT The BIU does not queue DRAM refresh requests. If the Refresh Control Unit generates another request before the BIU handles the present request, the BIU loses the present request. However, the address associated with the request is not lost. The refresh address changes only after the BIU runs a refresh bus cycle.
REFRESH CONTROL UNIT 7.5 REFRESH BUS CYCLES Refresh bus cycles look exactly like ordinary memory read bus cycles except for the control signals listed in Table 7-1. These signals can be ANDed in a DRAM controller to detect a refresh bus cycle. The 16-bit bus processor drives both the BHE and A0 pins high during refresh cycles. The 8-bit bus version replaces the BHE pin with RFSH, which has the same timings. The 8-bit bus processor drives RFSH low and A0 high during refresh cycles. Table 7-1.
REFRESH CONTROL UNIT T4 T1 T2 T3/TW T4 CLKOUT Muxed Address Row Column S2:0 CS RAS 1 CAS 2 WE NOTES: 1. CAS is unnecessary for refresh cycles only. 2. WE is necessary for write cycles only. A1267-0A Figure 7-4. Suggested DRAM Control Signal Timing Relationships The cycle begins with presentation of the row address. RAS should go active on the falling edge of T2. At the rising edge of T2, the address lines should switch to a column address. CAS goes active on the falling edge of T3.
REFRESH CONTROL UNIT 7.7 PROGRAMMING THE REFRESH CONTROL UNIT Given a specific processor operating frequency and information about the DRAMs in the system, the user can program the Refresh Control Unit registers. 7.7.1 Calculating the Refresh Interval DRAM data sheets show DRAM refresh requirements as a number of refresh cycles necessary and the maximum period to run the cycles. (The number of refresh cycles is the same as the number of rows.
REFRESH CONTROL UNIT 7.7.2.1 Refresh Base Address Register The Refresh Base Address Register (Figure 7-6) programs the base (upper seven bits) of the refresh address. Seven-bit mapping places the refresh address at any 4 Kbyte boundary within the 1 Mbyte address space. When the partial refresh address from the 9-bit address counter (see Figure 7-1 and “Refresh Control Unit Capabilities” on page 7-2) passes 1FFH, the Refresh Control Unit does not increment the refresh base address.
REFRESH CONTROL UNIT Register Name: Refresh Clock Interval Register Register Mnemonic: RFTIME Register Function: Sets refresh rate. 15 0 R C 8 R C 7 R C 6 R C 5 R C 4 R C 3 R C 2 R C 1 R C 0 A1288-0A Bit Mnemonic RC8:0 Refresh Counter Reload Value NOTE: Reset State Bit Name 000H Function Sets the desired clock count between refresh cycles. Reserved register bits are shown with gray shading.
REFRESH CONTROL UNIT Register Name: Refresh Control Register Register Mnemonic: RFCON Register Function: Controls Refresh Unit operation. 15 0 R C 8 R E N R C 7 R C 6 R C 5 R C 4 R C 3 R C 2 R C 1 R C 0 A1311-0A Bit Mnemonic Bit Name Reset State Function REN Refresh Control Unit Enable 0 Setting REN enables the Refresh Unit. Clearing REN disables the Refresh Unit. RC8:0 Refresh Counter 000H These bits contain the present value of the down-counter that triggers refresh requests.
REFRESH CONTROL UNIT $mod186 name example_80C186_RCU_code ; FUNCTION: This function initializes the DRAM Refresh ; Control Unit to refresh the DRAM starting at dram_addr ; at clock_time intervals. ; SYNTAX: ; extern void far config_rcu(int dram_addr, int clock_time); ; INPUTS: ; dram_addr - Base address of DRAM to refresh clock_time - DRAM refresh rate ; OUTPUTS: None ; ; NOTE: Parameters are passed on the stack as required by high-level languages.
REFRESH CONTROL UNIT mov mov out dx, RFBASE ax, _dram_addr dx, al ;set upper 7 address bits mov mov out dx, RFTIME ax, _clock_time dx, al ;set clock pre_scaler mov mov out dx, RFCON ax, Enable dx, al ;Enable RCU mov cx, 8 xor di, di ;8 dummy cycles are ;required by DRAMs ;before actual use _exercise_ram: mov word ptr [di], 0 loop _exercise_ram pop pop pop pop pop _config_rcu lib_80186 di dx cx ax bp ;restore saved registers ;restore caller’s bp ret endp ends end Example 7-1.
REFRESH CONTROL UNIT T1 T1 T1 T1 T1 T4 T1 CLKOUT 3 1 4 HOLD 2 HLDA 6 AD15:0 DEN RD, WR, BHE, S2:0 DT / R, A19:16 5 NOTES: 1. HLDA is deasserted; signaling need to run DRAM refresh cycles less than TCLHAV. 2. External bus master terminates use of the bus. 3. HOLD deasserted; greater than THVCL. 4. Hold may be reasserted after one clock. 5. Lines come out of float in order to run DRAM refresh cycle. A1534-0A Figure 7-9.
8 Interrupt Control Unit
CHAPTER 8 INTERRUPT CONTROL UNIT The 80C186 Modular Core has a single maskable interrupt input. (See “Interrupts and Exception Handling” on page 2-39.) The Interrupt Control Unit (ICU) expands the interrupt capabilities beyond a single input. To fulfill this function, the Interrupt Control Unit operates in either of two modes: Master or Slave. In Master mode, the ICU controls the maskable interrupt input to the CPU. Interrupts can originate from the on-chip peripherals and from four external interrupt pins.
INTERRUPT CONTROL UNIT Interrupts eliminate the need for polling by signalling the CPU that a peripheral device requires servicing. The CPU then stops executing the main task, saves its state and transfers execution to the peripheral-servicing code (the interrupt handler). At the end of the interrupt handler, the CPU’s original state is restored and execution continues at the point of interruption in the main task. 8.
INTERRUPT CONTROL UNIT 8.2.1.1 Interrupt Masking There are circumstances in which a programmer may need to disable an interrupt source temporarily (for example, while executing a time-critical section of code or servicing a high-priority task). This temporary disabling is called interrupt masking. All interrupts from the Interrupt Control Unit can be masked either globally or individually.
INTERRUPT CONTROL UNIT The priority of each source is programmable. The Interrupt Control register enables the programmer to assign each source a priority that differs from the default. The priority must still be between zero (highest) and seven (lowest). Interrupt sources can be programmed to share a priority. The Interrupt Control Unit uses the default priorities (see Table 8-1) within the shared priority level to determine which interrupt to service first.
INTERRUPT CONTROL UNIT 8.3 FUNCTIONAL OPERATION IN MASTER MODE This section covers the process in which the Interrupt Control Unit receives interrupts and asserts the maskable interrupt request to the CPU. 8.3.1 Typical Interrupt Sequence When the Interrupt Control Unit first detects an interrupt, it sets the corresponding bit in the Interrupt Request register to indicate that the interrupt is pending. The Interrupt Control Unit checks all pending interrupt sources.
INTERRUPT CONTROL UNIT 8.3.2.1 Priority Resolution Example This example illustrates priority resolution.
INTERRUPT CONTROL UNIT 8.3.2.2 Interrupts That Share a Single Source Multiple interrupt requests can share a single interrupt input to the Interrupt Control Unit. (For example, the three timers share a single input.) Although these interrupts share an input, each has its own interrupt vector. (For example, when a Timer 0 interrupt occurs, the Timer 0 interrupt handler is executed.) This section uses the three timers as an example to describe how these interrupts are prioritized and serviced.
INTERRUPT CONTROL UNIT INT0 INT VCC 8259A or 82C59A INTA0 Interrupt Control Unit INTA INT1 INT VCC 8259A or 82C59A INTA INTA1 A1211-A0 Figure 8-2. Using External 8259A Modules in Cascade Mode 8.3.3.1 Special Fully Nested Mode Special fully nested mode is an optional feature normally used with cascade mode. It is applicable only to INT0 and INT1. In special fully nested mode, an interrupt request is serviced even if its In-Service bit is set.
INTERRUPT CONTROL UNIT 8.3.4 Interrupt Acknowledge Sequence During the interrupt acknowledge sequence, the Interrupt Control Unit passes the interrupt type to the CPU. The CPU then multiplies the interrupt type by four to derive the interrupt vector address in the interrupt vector table. (“Interrupt/Exception Processing” on page 2-39 describes the interrupt acknowledge sequence and Figure 2-25 on page 2-40 illustrates the interrupt vector table.
INTERRUPT CONTROL UNIT 8.3.6 Edge and Level Triggering The external interrupts (INT3:0) can be programmed for either edge or level triggering (see “Interrupt Control Registers” on page 8-12). Both types of triggering are active high. An edge-triggered interrupt is generated by a zero-to-one transition on an external interrupt pin. The pin must remain high until after the CPU acknowledges the interrupt, then must go low to reset the edgedetection circuitry.
INTERRUPT CONTROL UNIT Clocks Interrupt presented to control unit 5 Interrupt presented to CPU INTA IDLE INTA IDLE READ IP IDLE READ CS IDLE PUSH FLAGS IDLE PUSH CS PUSH IP IDLE First instruction fetch from interrupt routine 4 2 Cascade Mode Only 4 5 4 3 (5 if not cascade mode) 4 4 4 3 4 4 5 Total 55 A1212-A0 Figure 8-3. Interrupt Control Unit Latency and Response Time 8.
INTERRUPT CONTROL UNIT Table 8-3. Interrupt Control Unit Registers in Master Mode (Continued) Register Name 8.4.1 Offset Address In-Service 2CH Priority Mask 2AH Interrupt Mask 28H Poll Status 26H Poll 24H EOI 22H Interrupt Control Registers Each interrupt source has its own Interrupt Control register. The Interrupt Control register allows you to define the behavior of each interrupt source.
INTERRUPT CONTROL UNIT Register Name: Interrupt Control Register (internal sources) Register Mnemonic: TCUCON, DMA0CON, DMA1CON Register Function: Control register for the internal interrupt sources 15 0 M S K P M 2 P M 1 P M 0 A1213-A0 Bit Mnemonic Bit Name Reset State Function MSK Interrupt Mask 1 Clear to enable interrupts from this source. PM2:0 Priority Level 111 Defines the priority level for this source. NOTE: Reserved register bits are shown with gray shading.
INTERRUPT CONTROL UNIT . Register Name: Interrupt Control Register (non-cascadable pins) Register Mnemonic: I2CON, I3CON Register Function: Control register for the non-cascadable external internal interrupt pins 15 0 L V L M S K P M 2 P M 1 P M 0 A1214-A0 Bit Mnemonic LVL Bit Name Level-trigger Reset State 0 Function Selects the interrupt triggering mode: 0 = edge triggering 1 = level triggering. MSK Interrupt Mask 1 Clear to enable interrupts from this source.
INTERRUPT CONTROL UNIT Register Name: Interrupt Control Register (cascadable pins) Register Mnemonic: I0CON, I1CON Register Function: Control register interrupt pins for the cascadable 15 external 0 S F N M C A S L V L M S K P M 2 P M 1 P M 0 A1215-A0 Bit Mnemonic Bit Name Reset State Function SFNM Special Fully Nested Mode 0 Set to enable special fully nested mode. CAS Cascade Mode 0 Set to enable cascade mode.
INTERRUPT CONTROL UNIT 8.4.2 Interrupt Request Register The Interrupt Request register (Figure 8-7) has one bit for each interrupt source. When a source requests an interrupt, its Interrupt Request bit is set (without regard to whether the interrupt is masked). The Interrupt Request bit is cleared when the interrupt is acknowledged. An external interrupt pin must remain asserted until its interrupt is acknowledged.
INTERRUPT CONTROL UNIT Register Name: Interrupt Mask Register Register Mnemonic: IMASK Register Function: Masks individual interrupt sources 15 0 I N T 3 I N T 2 I N T 1 I N T 0 D M A 1 D M A 0 T M R A1202-A0 Bit Mnemonic Bit Name Reset State Function INT3:0 External Interrupt Mask 0000 0 Set a bit to mask (disable) interrupt requests from the corresponding external interrupt pin.
INTERRUPT CONTROL UNIT Register Name: Priority Mask Register Register Mnemonic: PRIMSK Register Function: Masks lower-priority interrupt sources 15 0 P M 2 P M 1 P M 0 A1216-A0 Bit Mnemonic PM2:0 NOTE: Bit Name Priority Mask Reset State 111 Function Defines a priority-based interrupt mask. Interrupts whose priority is lower than this value are masked. Reserved register bits are shown with gray shading.
INTERRUPT CONTROL UNIT Register Name: In-Service Register Register Mnemonic: INSERV Register Function: Indicates which interrupt handlers are in process 15 0 I N T 3 I N T 2 I N T 1 I N T 0 D M A 1 D M A 0 T M R A1192-A0 Bit Mnemonic Bit Name Reset State Function INT3:0 External Interrupt InService 0000 0 A bit is set to indicate that the corresponding external interrupt is being serviced.
INTERRUPT CONTROL UNIT Reading the Poll register (Figure 8-11) acknowledges the pending interrupt, just as if the CPU had started the interrupt vectoring sequence. The Interrupt Control Unit updates the Interrupt Request, In-Service, Poll, and Poll Status registers, as it does in the normal interrupt acknowledge sequence. However, the processor does not run an interrupt acknowledge sequence or fetch the vector from the vector table.
INTERRUPT CONTROL UNIT Register Name: Poll Status Register Register Mnemonic: POLLSTS Register Function: Read to check for pending interrupts when polling 15 0 V T 4 I R E Q V T 3 V T 2 V T 1 V T 0 A1209-A0 Bit Mnemonic Bit Name Reset State Function IREQ Interrupt Request 0 This bit is set to indicate a pending interrupt. VT4:0 Vector Type 0 Contains the interrupt type of the highest priority pending interrupt. NOTE: Reserved register bits are shown with gray shading.
INTERRUPT CONTROL UNIT Register Name: End-of-Interrupt Register Register Mnemonic: EOI Register Function: Used to issue an EOI command 15 0 V T 4 N S P E C V T 3 V T 2 V T 1 V T 0 A1210-A0 Bit Mnemonic Bit Name Reset State Function NSPEC Nonspecific EOI 0 Set to issue a nonspecific EOI. VT4:0 Interrupt Type 0 0000 Write with the interrupt type of the interrupt whose In-Service bit is to be cleared. NOTE: Reserved register bits are shown with gray shading.
INTERRUPT CONTROL UNIT Register Name: Interrupt Status Register Register Mnemonic: INTSTS Register Function: Indicates pending shared-source interrupts and DMA suspension 15 0 T M R 2 D H L T T M R 1 T M R 0 A1193-A0 Bit Mnemonic Bit Name Reset State Function DHLT DMA Halt 0 This bit is set to suspend DMA activity. TMR2:0 Timer Interrupt Pending 000 A bit is set to indicate a pending interrupt from the corresponding timer. NOTE: Reserved register bits are shown with gray shading.
INTERRUPT CONTROL UNIT INT0 INT VCC INTA 8259A/ 82C59A INTA 80186 Modular Core Select Cascade Address Decode IRQ A1194-A0 Figure 8-15.
INTERRUPT CONTROL UNIT DMA 0 Timer 0 Timer 1 Timer 2 DMA 1 Interrupt Priority Resolver Vector Generation Logic To External 8259A Interrupt Request F - Bus A1195-A0 Figure 8-16. Interrupt Sources in Slave Mode 8.5.1 Slave Mode Programming Some registers differ between Slave mode and Master mode.
INTERRUPT CONTROL UNIT 8.5.1.1 Interrupt Vector Register The Interrupt Vector Register is used only in Slave mode. In Master mode, the interrupt vector types are fixed; in Slave mode they are programmable. The Interrupt Vector Register is used to specify the five most-significant bits of the interrupt vector type. The three least-significant bits are fixed (Table 8-5). Table 8-4.
INTERRUPT CONTROL UNIT Register Name: Interrupt Vector Register (Slave Mode only) Register Mnemonic: INTVEC Register Function: Specifies the five most-significant bit of the interrupt vector types for the internal interrupt sources 15 0 T 4 T 3 T 2 T 1 T 0 A1196-A0 Bit Mnemonic T4:0 Bit Name Interrupt Vector Type Field NOTE: Reset State 00000 Function Specifies the five most-significant bits of the interrupt vector types for the internal interrupt sources.
INTERRUPT CONTROL UNIT Register Name: End-of-Interrupt Register (in Slave Mode) Register Mnemonic: EOI Register Function: Used to issue the EOI command 15 0 V T 2 V T 1 V T 0 A1197-A0 Bit Mnemonic VT2:0 NOTE: Bit Name Interrupt Type Reset State 0 Function Write the three LSBs of the interrupt type (see Table 8-5) to these bits to issue an EOI command in slave mode. Reserved register bits are shown with gray shading.
INTERRUPT CONTROL UNIT 8.5.2 Interrupt Vectoring in Slave Mode In Slave mode, the external 8259A module acts as the master interrupt controller. Therefore, interrupt acknowledge cycles are required for every interrupt, including those from integrated peripherals. During the first interrupt acknowledge cycle, the external 8259A determines which slave interrupt controller has the highest priority interrupt request. It then drives that slave’s address onto its CAS2:0 pins (Figure 8-20).
INTERRUPT CONTROL UNIT External interrupt acknowledge cycles must be run for every maskable interrupt. Therefore, the interrupt response time for every interrupt will be 55 clocks, as shown in Figure 8-21. Clocks Interrupt presented to Interrupt Control Unit 5 Interrupt presented to external 82C59A First instruction fetch from interrupt routine INTA IDLE INTA IDLE READ IP IDLE READ CS IDLE PUSH FLAGS IDLE PUSH CS PUSH IP IDLE 4 2 4 5 4 3 4 4 4 3 4 4 5 Total 55 A1200-A0 Figure 8-21.
INTERRUPT CONTROL UNIT 5. Set the mask bit in the Interrupt Mask register for any interrupts that you wish to disable. Example 8-1 shows sample code to initialize the Interrupt Control Unit. $mod186 name example_80C186_ICU_initialization ; ;This routine configures the interrupt controller to provide two cascaded ;interrupt inputs (through an external 8259A connected to INT0 and INTA0#) ;and two direct interrupt inputs connected to INT1 and INT3. The default ;priorities are used.
9 Timer/Counter Unit
CHAPTER 9 TIMER/COUNTER UNIT The Timer/Counter Unit can be used in many applications. Some of these applications include a real-time clock, a square-wave generator and a digital one-shot. All of these can be implemented in a system design. A real-time clock can be used to update time-dependent memory variables. A square-wave generator can be used to provide a system clock tick for peripheral devices.
TIMER/COUNTER UNIT T0 In T1 In Transition Latch/ Synchronizer Transition Latch/ Synchronizer Timer 0 Registers CPU Timer 1 Registers Timer 2 Registers CPU Clock Counter Element Output Latch T0 Out Output Latch T1 Out Interrupt Latch A1292-0A Figure 9-1.
TIMER/COUNTER UNIT Timer 0 Timer 1 Timer 2 Timer 0 Timer 1 Timer 2 Timer 0 Serviced Serviced Serviced Dead Serviced Serviced Serviced Dead Serviced 3 4 1 T0IN 2 5 T1IN T0OUT T1OUT NOTES: 1. T0IN resolution time (setup time met). 2. T1IN resolution time (setup time not met). 3. Modified count value written into Timer 0 count register. 4. T1IN resolution time, count value written into Timer 1 count register. 5. T1IN resolution time. A1293-0A Figure 9-2.
TIMER/COUNTER UNIT Timer Enabled (EN = 1) ? Start No Done Yes No No No Retrigger (RTG = 1) ? Yes Done Yes Lo to Hi transition on input pin since last service ? No Yes Clear Count Register No Yes Did Timer 2 Reach Maxcount Last Service State ? No Yes Yes Lo to Hi transition on input pin since last service ? No Timer Input at High Level ? Prescaler On (P = 1) ? External Clocking (EXT = 1) ? Done Yes Increment Counter Continued "A" A1294-0A Figure 9-3.
TIMER/COUNTER UNIT Continued From "A" Alternating Maxcount Regs (ALT = 1) ? No Counter = Compare "A" ? Yes (Use"A") Yes No Yes No No (Use"B") Using Maxcount A (RIU = 0) ? Counter = Compare "A" ? No Counter = Compare "B" ? Done Yes Pulse TOUT Pin Low For 1 Clock Yes Yes Set RIU Bit TOUT Pin Driven Low Clear RIU Bit TOUT Pin Driven High Yes Continuous Mode (CONT=1) ? Continuous Mode (CONT=1) ? No No No Interrupt Bit Set ? Clear Enable Bit (Stop Counting) Clear Enable Bit (Stop Coun
TIMER/COUNTER UNIT When configured for internal clocking, the Timer/Counter Unit uses the input pins either to enable timer counting or to retrigger the associated timer. Externally, a timer increments on low-tohigh transitions on its input pin (up to ¼ CLKOUT frequency). Timers 0 and 1 each have a single output pin. Timer output can be either a single pulse, indicating the end of a timing cycle, or a variable duty cycle wave.
TIMER/COUNTER UNIT Register Name: Timer 0 and 1 Control Registers Register Mnemonic: T0CON, T1CON Register Function: Defines Timer 0 and 1 operation. 15 E N 0 I N H I N T R I U M C R T G P E X T A L T C O N T A1297-0A Bit Mnemonic Bit Name Reset State Function EN Enable 0 Set to enable the timer. This bit can be written only when the INH bit is set. INH Inhibit X Set to enable writes to the EN bit. Clear to ignore writes to the EN bit.
TIMER/COUNTER UNIT Register Name: Timer 0 and 1 Control Registers Register Mnemonic: T0CON, T1CON Register Function: Defines Timer 0 and 1 operation. 15 0 I N H E N I N T R I U M C R T G P E X T A L T C O N T A1297-0A Bit Mnemonic Bit Name Reset State Function RTG Retrigger X This bit specifies the action caused by a low-to-high transition on the TMR INx input. Set RTG to reset the count; clear RTG to enable counting. This bit is ignored with external clocking (EXT=1).
TIMER/COUNTER UNIT Register Name: Timer 2 Control Register Register Mnemonic: T2CON Register Function: Defines Timer 2 operation. 15 E N 0 I N H I N T C O N T M C A1298-0A Bit Mnemonic Bit Name Reset State Function EN Enable 0 Set to enable the timer. This bit can be written only when the INH bit is set. INH Inhibit X Set to enable writes to the EN bit. Clear to ignore writes to the EN bit. The INH bit is not stored; it always reads as zero.
TIMER/COUNTER UNIT Register Name: Timer Count Register Register Mnemonic: T0CNT, T1CNT, T2CNT Register Function: Contains the current timer count. 15 T C 1 5 0 T C 1 4 T C 1 3 T C 1 2 T C 1 1 T C 1 0 T C 9 T C 8 T C 7 T C 6 T C 5 T C 4 T C 3 T C 2 T C 1 T C 0 A1299-0A Bit Mnemonic TC15:0 Bit Name Timer Count Value Reset State XXXXH Function Contains the current count of the associated timer. Figure 9-7.
TIMER/COUNTER UNIT Register Name: Timer Maxcount Compare Register Register Mnemonic: T0CMPA, T0CMPB, T1CMPA, T1CMPB, T2CMPA Register Function: Contains timer maximum count value. 15 T C 1 5 0 T C 1 4 T C 1 3 T C 1 2 T C 1 1 T C 1 0 T C 9 T C 8 T C 7 T C 6 T C 5 T C 4 T C 3 T C 2 T C 1 T C 0 A1300-0A Bit Mnemonic TC15:0 Bit Name Timer Compare Value Reset State XXXXH Function Contains the maximum value a timer will count to before resetting its Count register to zero. Figure 9-8.
TIMER/COUNTER UNIT 9.2.2 Clock Sources The 16-bit Timer Count register increments once for each timer event. A timer event can be a low-to-high transition on a timer input pin (Timers 0 and 1), a pulse generated every fourth CPU clock (all timers) or a timeout of Timer 2 (Timers 0 and 1). Up to 65536 (216) events can be counted. Timers 0 and 1 can be programmed to count low-to-high transitions on their input pins as timer events by setting the External (EXT) bit in their control registers.
TIMER/COUNTER UNIT The timer counting from its initial count (usually zero) to its maximum count (either Maxcount Compare A or B) and resetting to zero defines one timing cycle. A Maxcount Compare value of 0 implies a maximum count of 65536, a Maxcount Compare value of 1 implies a maximum count of 1, etc. Only equivalence between the Timer Count and Maxcount Compare registers is checked. The count does not reset to zero if its value is greater than the maximum count.
TIMER/COUNTER UNIT Table 9-2. Timer Retriggering EXT RTG Timer Operation 0 0 Timer counts internal events, if input pin remains high. 0 1 Timer counts internal events; count resets to zero on every low-to-high transition on the input pin. 1 X Timer input acts as clock source. When the EXT bit is clear and the RTG bit is set, every low-to-high transition on the timer input pin causes the Count register to reset to zero.
TIMER/COUNTER UNIT Timer 0 Serviced 1 Internal Count Value Maxcount - 1 0 TxOUT Pin NOTE: 1. TCLOV1 A1301-0A Figure 9-9. TxOUT Signal Timing In dual maximum count mode, the timer output pin indicates which Maxcount Compare register is currently in use. A low output indicates Maxcount Compare B, and a high output indicates Maxcount Compare A (see Figure 9-4 on page 9-6). If programmed to run continuously, a repetitive waveform can be generated.
TIMER/COUNTER UNIT The input pins for Timers 0 and 1 provide an alternate method for enabling and disabling timer counting. When using internal clocking, the input pin can be programmed either to enable the timer or to reset the timer count, depending on the state of the Retrigger (RTG) bit in the control register. When used as an enable function, the input pin either allows (input high) or prevents (input low) timer counting. To ensure recognition of an input level, it must be valid for four CPU clocks.
TIMER/COUNTER UNIT 9.3.2 Synchronization and Maximum Frequency All timer inputs are latched and synchronized with the CPU clock. Because of the internal logic required to synchronize the external signals, and the multiplexing of the counter element, the Timer/Counter Unit can operate only up to ¼ of the CLKOUT frequency. Clocking at greater frequencies will result in missed clocks. 9.3.2.
TIMER/COUNTER UNIT $mod186 name example_80186_family_timer_code ;FUNCTION: ; ; ; ; ; ; ; ;SYNTAX: ; ;INPUTS: ; ; ; ; ;OUTPUTS: This function sets up the timer and interrupt controller to cause the timer to generate an interrupt every 10 milliseconds and to service interrupts to implement a real time clock. ;NOTE: ; ; ; ; ; ; ; ; ; ; ; Parameters are passed on the stack as required by high-level languages Timer 2 is used in this example because no input or output signals are required.
TIMER/COUNTER UNIT lib_80186 segment public ’code’ assume cs:lib_80186, ds:data public _set_time _set_time proc far push mov bp bp, sp ;save caller’s bp ;get current top of stack hour equ word ptr[bp+6] ;get parameters off stack minute equ word ptr[bp+8] second equ word ptr[bp+10] T2Compare equ word ptr[bp+12] push push push ax dx si ;save registers used push xor mov mov mov ds ax, ax ;set interrupt vector ds, ax si, 4*timer_2_int word ptr ds:[si], offset timer_2_interrupt_routine inc si inc si mov
TIMER/COUNTER UNIT sti ;enable interrupts pop si pop dx pop ax pop bp ret _set_time endp ;restore saved registers ;restore caller’s bp timer_2_interrupt_routine proc far push push cmp jae inc jmp ax dx _msec, 99 bump_second _msec short reset_int_ctl bump_second: mov _msec, 0 cmp _minute, 59 jae bump_minute inc _second jmp short reset_int_ctl bump_minute: mov _second, 0 cmp _minute, 59 jae bump_hour inc _minute jmp short reset_int_ctl bump_hour: mov cmp jae inc jmp _minute, 0 _hour, 12 reset_hour _ho
TIMER/COUNTER UNIT $mod186 name ;FUNCTION: ; ; ; SYNTAX: ; ; INPUTS: ; ; ; ; ; ; ; ; OUTPUTS: ; ; NOTE: ; T1CMPA T1CMPB T1CNT T1CON example_timer1_square_wave_code This function generates a square wave of given frequency and duty cycle on Timer 1 output pin. extern void far clock(int mark, int space) mark - This is the mark (1) time. space - This is the space (0) time. The register compare value for a given time can be easily calculated from the formula below.
TIMER/COUNTER UNIT pop pop pop pop ret _clock lib_80186 end dx bx ax ;restore saved registers bp ;restore caller’s bp endp ends Example 9-2. Configuring a Square-Wave Generator (Continued) $mod186 name example_timer1_1_shot_code ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; FUNCTION: This function generates an active-low one-shot pulse on Timer 1 output pin. SYNTAX: extern void far one_shot(int CMPB); INPUTS: CMPB - This is the T1CMPB value required to generate a pulse of a given pulse width.
TIMER/COUNTER UNIT _CMPB equ word ptr[bp+6] ;get parameter off the stack push push mov xor out mov mov out mov mov out mov mov out ax dx dx, ax, dx, dx, ax, dx, dx, ax, dx, dx, ax, dx, ;save registers that will be ;modified ;Clear Timer 1 Counter T1CNT ax al T1CMPA 1 al T1CMPB _CMPB al T1CON C002H al ;set time before t_shot to 0 ;set pulse time ;start Timer 1 CountDown: test jz and out in ax, dx ax, MaxCount CountDown ax, not MaxCount dx, al ;read in T1CON ;max count occurred? ;no: then wait ;cl
10 Direct Memory Access Unit
CHAPTER 10 DIRECT MEMORY ACCESS UNIT In many applications, large blocks of data must be transferred between memory and I/O space. A disk drive, for example, usually reads and writes data in blocks that may be thousands of bytes long. If the CPU were required to handle each byte of the transfer, the main tasks would suffer a severe performance penalty. Even if the data transfers were interrupt driven, the overhead for transferring control to the interrupt handler would still decrease system throughput.
DIRECT MEMORY ACCESS UNIT When the DMA request is granted, the Bus Interface Unit provides the bus signals for the DMA transfer, while the DMA channel provides the address information for the source and destination devices. The DMA Unit does not provide a discrete DMA acknowledge signal, unlike other DMA controller chips (an acknowledge can be synthesized, however). The DMA channel continues transferring data as long as the request is active and it has not exceeded its programmed transfer limit.
DIRECT MEMORY ACCESS UNIT 10.1.1.1 DMA Transfer Directions The source and destination addresses for a DMA transfer are programmable and can be in either memory or I/O space. DMA transfers can be programmed for any of the following four directions: • • • • from memory space to I/O space from I/O space to memory space from memory space to memory space from I/O space to I/O space DMA transfers can access the Peripheral Control Block. 10.1.1.
DIRECT MEMORY ACCESS UNIT 10.1.4 External Requests External DMA requests are asserted on the DRQ pins. The DRQ pins are sampled on the falling edge of CLKOUT. It takes a minimum of four clocks before the DMA cycle is initiated by the BIU (see Figure 10-2). The DMA request is cleared four clocks before the end of the DMA cycle (effectively re-arming the DRQ input). T1 or TW or TI T2 or TW or TI T3 or TW or TI T4 or TI T1 of DMA Cycle 4 DRQ 1 2 3 NOTES: 1. TINVCL : DMA request to clock low. 2.
DIRECT MEMORY ACCESS UNIT 10.1.4.1 Source Synchronization A typical source-synchronized transfer is shown in Figure 10-3. Most DMA-driven peripherals deassert their DRQ line only after the DMA transfer has begun. The DRQ signal must be deasserted at least four clocks before the end of the DMA transfer (at the T1 state of the deposit phase) to prevent another DMA cycle from occurring.
DIRECT MEMORY ACCESS UNIT Deposit Cycle Fetch Cycle T1 T2 T3 T4 T1 T2 T3 T4 TI TI CLKOUT DRQ (Case 1) 1 DRQ (Case 2) 2 NOTES: 1. Current destination synchronized transfer will not be immediately followed by another DMA transfer. 2. Current destination synchronized transfer will be immediately followed by another DMA transfer. A1189-0A Figure 10-4. Destination-Synchronized Transfers 10.1.5 Internal Requests Internal DMA requests can come from either Timer 2 or the system software. 10.1.5.
DIRECT MEMORY ACCESS UNIT 10.1.6 DMA Transfer Counts Each DMA Unit maintains a programmable 16-bit transfer count value that controls the total number of transfers the channel runs. The transfer count is decremented by one after each transfer (regardless of data size). The DMA channel can be programmed to terminate transfers when the transfer count reaches zero (also referred to as terminal count). 10.1.
DIRECT MEMORY ACCESS UNIT 10.1.8 DMA Unit Interrupts Each DMA channel can be programmed to generate an interrupt request when its transfer count reaches zero. 10.1.9 DMA Cycles and the BIU The DMA Unit uses the Bus Interface Unit to perform its transfers. When the DMA Unit has a pending request, it signals the BIU. If the BIU has no other higher-priority request pending, it runs the DMA cycle. (BIU priority is described in Chapter 3, “Bus Interface Unit.
DIRECT MEMORY ACCESS UNIT The last point is extremely important when the two channels use different synchronization. For example, consider the case in which channel 1 is programmed for high priority and destination synchronization and channel 0 is programmed for low priority and source synchronization. If a DMA request occurs for both channels simultaneously, channel 1 performs the first transfer. At the end of channel 1’s deposit cycle, two idle states are inserted (thus releasing the bus).
DIRECT MEMORY ACCESS UNIT Both Requests Asserted Channel 0 1 Priority Low Low Synch SRC SRC Channel 1 Channel 0 Channel 1 Channel 0 Channel 0 1 Priority High Low Synch SRC SRC Channel 0 Channel 0 Channel 0 1 Priority High Low Synch Dest SRC Channel 0 Etc. Etc. Channel 1 Channel 1 Channel 0 Completes All Transfers Channel 1 Channel 0 Etc. Channel 1 Destination Synch Releases Bus A1190-0A Figure 10-6. Examples of DMA Priority 10.1.10.1.
DIRECT MEMORY ACCESS UNIT Two 16-bit Peripheral Control Block registers define each of the 20-bit pointers. Figures 10.7 and 10.8 show the layout of the DMA Source Pointer address registers, and Figures 10.9 and 10.10 show the layout of the DMA Destination Pointer address registers. The DSA19:16 and DDA19:16 (high-order address bits) are driven on the bus even if I/O transfers have been programmed.
DIRECT MEMORY ACCESS UNIT Register Name: DMA Source Address Pointer (Low) Register Mnemonic: DxSRCL Register Function: Contains the lower 16 bits of the DMA Source pointer.
DIRECT MEMORY ACCESS UNIT Register Name: DMA Destination Address Pointer (High) Register Mnemonic: DxDSTH Register Function: Contains the upper 4 bits of the DMA Destination pointer. 15 0 D D A 1 9 D D A 1 8 D D A 1 7 D D A 1 6 A1178-0A Bit Mnemonic DDA19:16 NOTE: Bit Name DMA Destination Address Reset State XXXXH Function DDA19:16 are driven on A19:16 during the deposit phase of a DMA transfer. Reserved register bits are shown with gray shading.
DIRECT MEMORY ACCESS UNIT Register Name: DMA Destination Address Pointer (Low) Register Mnemonic: DxDSTL Register Function: Contains the lower 16 bits of the DMA Destination pointer.
DIRECT MEMORY ACCESS UNIT Register Name: DMA Control Register Register Mnemonic: DxCON Register Function: Controls DMA channel parameters. 15 0 D M E M D D E C D I N C S I N C S D E C S M E M T C I N T S Y N 1 S Y N 0 P I D R Q C H G S T R T W O R D A1180-0A Bit Mnemonic Bit Name Reset State Function DMEM Destination Address Space Select X Selects memory or I/O space for the destination pointer. Set DMEM to select memory space; clear DMEM to select I/O space.
DIRECT MEMORY ACCESS UNIT Register Name: DMA Control Register Register Mnemonic: DxCON Register Function: Controls DMA channel parameters. 15 0 D M E M D D E C D I N C S M E M S I N C S D E C T C I N T S Y N 1 S Y N 0 P I D R Q C H G S T R T W O R D A1180-0A Bit Mnemonic Bit Name Reset State Function TC Terminal Count X Set TC to terminate transfers on Terminal Count.
DIRECT MEMORY ACCESS UNIT Register Name: DMA Control Register Register Mnemonic: DxCON Register Function: Controls DMA channel parameters. 15 0 D M E M D D E C D I N C S M E M S I N C S D E C T C I N T S Y N 1 S Y N 0 P I D R Q C H G S T R T W O R D A1180-0A Bit Mnemonic Bit Name Reset State Function CHG Change Start Bit X Set CHG to enable modifying the STRT bit. STRT Start DMA Channel 0 Set STRT to arm the DMA channel.
DIRECT MEMORY ACCESS UNIT 10.2.1.4 Arming the DMA Channel Each DMA channel must be armed before it can recognize DMA requests. A channel is armed by setting its STRT (Start) bit in the DMA Control Register (Figure 10-11 on page 10-15). The STRT bit can be modified only if the CHG (Change Start) bit is set at the same time. The CHG bit is a safeguard to prevent accidentally arming a DMA channel while modifying other channel parameters. A DMA channel is disarmed by clearing its STRT bit.
DIRECT MEMORY ACCESS UNIT Register Name: DMA Transfer Count Register Mnemonic: DxTC Register Function: Contains the DMA channel’s transfer count. 15 T C 1 5 0 T C 1 4 T C 1 3 T C 1 1 T C 1 2 T C 1 0 T C 9 T C 8 T C 7 T C 6 T C 5 T C 4 T C 3 T C 2 T C 1 T C 0 A1172-0A Bit Mnemonic TC15:0 Bit Name Transfer Count Reset State XXXXH Function Contains the transfer count for a DMA channel. This value is decremented by one after each transfer. Figure 10-12.
DIRECT MEMORY ACCESS UNIT 10.2.2 Suspension of DMA Transfers Whenever the CPU receives an NMI, all DMA activity is suspended at the end of the current transfer. The CPU suspends DMA activity by setting the DHLT bit in the Interrupt Status Register (Figure 8-14 on page 8-23). When an IRET instruction is executed, the CPU clears the DHLT bit and DMA transfers are allowed to resume. Software can read and write the DHLT bit. NOTE Do not write to the DHLT bit while Timer/Counter Unit interrupts are enabled.
DIRECT MEMORY ACCESS UNIT 10.3.2 DMA Latency DMA Latency is the delay between a DMA request being asserted and the DMA cycle being run. The DMA latency for a channel is controlled by many factors: • Bus HOLD — Bus HOLD takes precedence over internal DMA requests. Using bus HOLD will degrade DMA latency. • LOCKed Instructions — Long LOCKed instructions (e.g., LOCK REP MOVS) will monopolize the bus, preventing access by the DMA Unit.
DIRECT MEMORY ACCESS UNIT 10.3.4 Generating a DMA Acknowledge The DMA channels do not provide a distinct DMA acknowledge signal. A chip-select line can be programmed to activate for the memory or I/O range that requires the acknowledge. The chipselect must be programmed to activate only when a DMA is in progress. Latched status line S6 can be used as a qualifier to the chip-select for situations in which the chip-select line will be active for both DMA and normal data accesses. 10.
DIRECT MEMORY ACCESS UNIT $MOD186 name ; ; ; ; DMA_EXAMPLE_1 This example shows code necessary to set up two DMA channels. One channel performs an unsynchronized transfer from memory to memory. The second channel is used by a hard disk controller located in I/O space. ; It is assumed that the constants for PCB register addresses are ; defined elsewhere with EQUates.
DIRECT MEMORY ACCESS UNIT MOV MOV OUT DX, D0DSTH AX, BX DX, AX ; GET HIGH NIBBLE ; THE POINTER ADDRESSES HAVE BEEN SET UP. NOW WE SET UP THE TRANSFER COUNT. MOV AX, 29 ; THE MESSAGE IS 29 BYTES LONG. MOV DX, D0TC ; XFER COUNT REG OUT DX, AX ; NOW WE NEED TO SET THE PARAMETERS FOR THE CHANNEL AS FOLLOWS: ; ; DESTINATION SOURCE ; ---------------; MEMORY SPACE MEMORY SPACE ; INCREMENT PTR INCREMENT PTR ; ; TERMINATE ON TC, NO INTERRUPT, UNSYNCHRONIZED, LOW PRIORITY RELATIVE ; TO CHANNEL 1, BYTE XFERS.
DIRECT MEMORY ACCESS UNIT MOV AX, 512 ; THE DISK READS IN 512 BYTE MOV OUT DX, D1TC DX, AX ; XFER COUNT REG SECTORS ; NOW WE NEED TO SET THE PARAMETERS FOR THE CHANNEL AS FOLLOWS: ; ; DESTINATION SOURCE ; ---------------; MEMORY SPACE I/O SPACE ; INCREMENT PTR CONSTANT PTR ; ; TERMINATE ON TC, INTERRUPT, SOURCE SYNC, HIGH PRIORITY RELATIVE TO ; CHANNEL 0, BYTE XFERS, USE DRQ PIN FOR REQUEST SOURCE. ARM CHANNEL.
DIRECT MEMORY ACCESS UNIT $mod186 name DMA_EXAMPLE_1 ; This example sets up the DMA Unit to perform a transfer from memory to ; I/O space every 22 uS. The data is sent to an A/D converter. ; It is assumed that the constants for PCB register addresses are ; defined elsewhere with EQUates. CODE_SEG SEGMENT ASSUME CS:CODE_SEG START: MOV AX, DATA_SEG MOV DS, AX ASSUME DS:DATA_SEG ; DATA SEGMENT POINTER ; First, set up the pointers. The source is in memory.
DIRECT MEMORY ACCESS UNIT ; NOW WE NEED TO SET THE PARAMETERS FOR THE CHANNEL AS FOLLOWS: ; ; DESTINATION SOURCE ; ---------------; I/O SPACE MEMORY SPACE ; CONSTANT PTR INCREMENT PTR ; ; TERMINATE ON TC, INTERRUPT, SOURCE SYNCHRONIZE, INTERNAL REQUESTS, ; LOW PRIORITY RELATIVE TO CHANNEL 1, BYTE XFERS. MOV MOV OUT AX, 0001011101010110B DX, D0CON DX, AX ; NOW WE ASSUME THAT TIMER 2 HAS BEEN PROPERLY PROGRAMMED FOR A 22uS DELAY. ; WHEN THE TIMER IS STARTED, A DMA TRANSFER WILL OCCUR EVERY 22uS.
11 Math Coprocessing
CHAPTER 11 MATH COPROCESSING The 80C186 Modular Core Family meets the need for a general-purpose embedded microprocessor. In most data control applications, efficient data movement and control instructions are foremost and arithmetic performed on the data is simple. However, some applications do require more powerful arithmetic instructions and more complex data types than those provided by the 80C186 Modular Core. 11.
MATH COPROCESSING The core has an Escape Trap (ET) bit in the PCB Relocation Register (Figure 4-1 on page 4-2) to control the availability of math coprocessing. If the ET bit is set, an attempted numerics execution results in a Type 7 interrupt. The 80C187 will not work with the 8-bit bus version of the processor because all 80C187 accesses must be 16-bit. The 80C188 Modular Core automatically traps ESC (numerics) opcodes to the Type 7 interrupt, regardless of Relocation Register programming. 11.
MATH COPROCESSING 11.3.1.1 Data Transfer Instructions Data transfer instructions move operands between elements of the 80C187 register stack or between stack top and memory. Instructions can convert any data type to temporary real and load it onto the stack in a single operation. Conversely, instructions can convert a temporary real operand on the stack to any data type and store it to memory in a single operation. Table 11-1 summarizes the data transfer instructions. Table 11-1.
MATH COPROCESSING Available data types include temporary real, long real, short real, short integer and word integer. The 80C187 performs automatic type conversion to temporary real. Table 11-2.
MATH COPROCESSING 11.3.1.3 Comparison Instructions Each comparison instruction (see Table 11-3) analyzes the stack top element, often in relationship to another operand. Then it reports the result in the Status Word condition code. The basic operations are compare, test (compare with zero) and examine (report tag, sign and normalization). Table 11-3. 80C187 Comparison Instructions 11.3.1.
MATH COPROCESSING 11.3.1.5 Constant Instructions Each constant instruction (see Table 11-5) loads a commonly used constant onto the stack. The values have full 80-bit precision and are accurate to about 19 decimal digits. Since a temporary real constant occupies 10 memory bytes, the constant instructions, only 2 bytes long, save memory space. Table 11-5. 80C187 Constant Instructions 11.3.1.6 FLDZ Load + 0.1 FLD1 Load +1.
MATH COPROCESSING 11.3.2 80C187 Data Types The microprocessor/math coprocessor combination supports seven data types: • Word Integer — A signed 16-bit numeric value. All operations assume a 2’s complement representation. • Short Integer — A signed 32-bit numeric value (double word). All operations assume a 2’s complement representation. • Long Integer — A signed 64-bit numeric value (quad word). All operations assume a 2’s complement representation.
MATH COPROCESSING Increasing Significance Word Integer Short Integer (Two's Complement) S Magnitude 15 0 S Magnitude (Two's Complement) 31 Long Integer 0 (Two's Complement) Magnitude S 63 Packed Decimal S 79 Short Real Long Real 0 Magnitude X d d d d d d d d 17 16 15 14 13 12 11 10 9 d 8 d 7 d d 6 5 d 4 d 3 d d d 2 1 0 72 Biased Exponent 31 23 S S d Significand 0 I Biased Exponent Significand 63 52 Temporary Real S 79 Biased Exponent 0 I I 64 63 Significand 0 NOT
MATH COPROCESSING Latch A1 CMD0 AD15:0 ALE A2 EN CMD1 External Oscillator CKM CLK CLKOUT 1 2 80C187 80C186 Modular Core RESET RESET WR NPWR RD NPRD BUSY BUSY ERROR ERROR PEREQ PEREQ NCS NPS1 NPS2 D15:0 A1529-0A Figure 11-2.
MATH COPROCESSING 11.4.1 Clocking the 80C187 The microprocessor and math coprocessor operate asynchronously, and their clock rates may differ. The 80C187 has a CKM pin that determines whether it uses the input clock directly or divided by two. Direct clocking works up to 12.5 MHz, which makes it convenient to feed the clock input from the microprocessor’s CLKOUT pin. Beyond 12.5 MHz, the 80C187 must use a multiplyby-two clock input up to a maximum of 32 MHz.
MATH COPROCESSING Bus cycles involving the 80C187 Math Coprocessor behave exactly like other I/O bus cycles with respect to the processor’s control pins. See “System Design Tips” for information on integrating the 80C187 into the overall system. 11.4.3 System Design Tips All 80C187 operations require that bus ready be asserted. The simplest way to return the ready indication is through hardware connected to the processor’s external ready pin.
MATH COPROCESSING Latch A15:0 ALE EN CMD0 AD15:0 Buffer A2 A1 D15:8 CMD1 External Oscillator 1 CKM CLKOUT T OE CLK 2 80C187 80C186 Modular Core RESET RESET WR NPWR RD NPRD BUSY BUSY Buffer D7:0 ERROR ERROR PEREQ PEREQ NCS T OE NPS1 CS DEN NPS2 DT/R D15:0 A1530-0A Figure 11-3.
MATH COPROCESSING 11.4.4 Exception Trapping The 80C187 detects six error conditions that can occur during instruction execution. The 80C187 can apply default fix-ups or signal exceptions to the microprocessor’s ERROR pin. The processor tests ERROR at the beginning of numerics instructions, so it traps an exception on the next attempted numerics instruction after it occurs. When ERROR tests active, the processor executes a Type 16 interrupt.
MATH COPROCESSING 80C186 Modular Core ERROR RESET CSx INTx Latch BUSY PEREQ ALE EN NCS A19:A16 AD15:0 RD WR CLKOUT A d d r e s s D D15:0 A2 A1 C '74 S D15:0 CLK CMD1 NPWR CMD0 Q Q NPRD 80C187 A19:0 NPS1 CKM PEREQ BUSY NPS2 D C Q '74 S ERROR RESET A1531-0A Figure 11-4.
MATH COPROCESSING $mod186 name example_80C187_init ; ;FUNCTION: This function initializes the 80C187 numerics coprocessor. ; ;SYNTAX: extern unsigned char far 187_init(void); ; ;INPUTS: None ; ;OUTPUTS: unsigned char - 0000h -> False -> coprocessor not initialized ; ffffh -> True -> coprocessor initialized ; ;NOTE: Parameters are passed on the stack as required by ; high-level languages.
MATH COPROCESSING $mod186 $modc187 name example_80C187_proc ;DESCRIPTION: This code section uses the 80C187 FSINCOS transcendental ; instruction to convert the locus of a point from polar ; to Cartesian coordinates. ; ;VARIABLES: The variables consist of the radius, r, and the angle, theta. ; Both are expressed as 32-bit reals and 0 <= theta <= pi/4. ; ;RESULTS: The results of the computation are the coordinates x and y ; expressed as 32-bit reals. ; ;NOTES: This routine is coded for Intel ASM86.
12 ONCE Mode
CHAPTER 12 ONCE MODE ONCE (pronounced “ahnce”) Mode provides the ability to three-state all output, bidirectional, or weakly held high/low pins except OSCOUT. To allow device operation with a crystal network, OSCOUT does not three-state. ONCE Mode electrically isolates the device from the rest of the board logic. This isolation allows a bed-of-nails tester to drive the device pins directly for more accurate and thorough testing.
ONCE MODE RES 2 UCS LCS All output, bidirectional, weakly held pins except OSCOUT 1 3 NOTES: 1. Entering ONCE Mode. 2. Latching ONCE Mode. 3. Leaving ONCE Mode (assuming 2 occurred). A1532-0A Figure 12-1.
A 80C186 Instruction Set Additions and Extensions
APPENDIX A 80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS The 80C186 Modular Core family instruction set differs from the original 8086/8088 instruction set in two ways. First, several instructions that were not available in the 8086/8088 instruction set have been added. Second, several 8086/8088 instructions have been enhanced for the 80C186 Modular Core family instruction set. A.
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS A.1.2 String Instructions INS source_string, port INS (in string) performs block input from an I/O port to memory. The port address is placed in the DX register. The memory address is placed in the DI register. This instruction uses the ES segment register (which cannot be overridden). After the data transfer takes place, the pointer register (DI) increments or decrements, depending on the value of the Direction Flag (DF).
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS The following listing gives the formal definition of the ENTER instruction for all cases. LEVEL denotes the value of the second operand. Push BP Set a temporary value FRAME_PTR: = SP If LEVEL > 0 then Repeat (LEVEL - 1) times: BP:=BP - 2 Push the word pointed to by BP End Repeat Push FRAME_PTR End if BP:=FRAME_PTR SP:=SP - first operand Figure A-1.
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS Main Program (Lexical Level 1) Procedure A (Lexical Level 2) Procedure B (Lexical Level 3) Procedure C (Lexical Level 3) Procedure D (Lexical Level 4) A1001-0A Figure A-2. Variable Access in Nested Procedures The first ENTER, executed in the Main Program, allocates dynamic storage space for Main, but no pointers are copied. The only word in the display points to itself because no previous value exists to return to after LEAVE is executed (see Figure A-3).
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS 15 0 Old BP BPM BP BPM BPM BPA* Display A Dynamic Storage A SP *BPA = BP Value for Procedure A A1003-0A Figure A-4. Stack Frame for Procedure A at Level 2 After Procedure A calls Procedure B, ENTER creates the display for Procedure B. The first word of the display points to the previous value of BP (BPA). The second word points to the value of BP for MAIN (BPM). The third word points to the BP for Procedure A (BPA).
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS 15 0 Old BP BPM BPM BPM BPA BP BPA BPM Display B BPA BPB Dynamic Storage B SP A1004-0A Figure A-5.
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS 15 0 Old BP BPM BPM BPM BPA BPA BPM BPA BPB BP BPB BPM BPA Display C BPC Dynamic Storage C SP A1005-0A Figure A-6. Stack Frame for Procedure C at Level 3 Called from B LEAVE LEAVE reverses the action of the most recent ENTER instruction. It collapses the last stack frame created. First, LEAVE copies the current BP to the Stack Pointer, releasing the stack space allocated to the current procedure.
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS BOUND register, address BOUND verifies that the signed value in the specified register lies within specified limits. If the value does not lie within the bounds, an array bounds exception (type 5) occurs. BOUND is useful for checking array bounds before attempting to access an array element. This prevents the program from overwriting information outside the limits of the array. BOUND has two operands. The first, register, specifies the register being tested.
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS A.2.2 Arithmetic Instructions IMUL destination, source, data IMUL (integer immediate multiply, signed) allows a value to be multiplied by an immediate operand. IMUL requires three operands. The first, destination, is the register where the result will be placed. The second, source, is the effective address of the multiplier. The source may be the same register as the destination, another register or a memory location.
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS A.2.3.2 Rotate Instructions ROL destination, count ROL (immediate rotate left) rotates the destination byte or word left by an immediate value. ROL has two operands. The first, destination, is the effective address to be rotated. The second, count, is an immediate byte value representing the number of rotations to be made. The most-significant bit of destination rotates into the least-significant bit.
B Input Synchronization
APPENDIX B INPUT SYNCHRONIZATION Many input signals to an embedded processor are asynchronous. Asynchronous signals do not require a specified setup or hold time to ensure the device does not incur a failure. However, asynchronous setup and hold times are specified in the data sheet to ensure recognition. Associated with each of these inputs is a synchronizing circuit (see Figure B-1) that samples the asynchronous signal and synchronizes it to the internal operating clock.
INPUT SYNCHRONIZATION A synchronization failure can occur when the output of the first latch does not meet the setup and hold requirements of the input of the second latch. The rate of failure is determined by the actual size of the sampling window of the data latch and by the amount of time between the strobe signals of the two latches. As the sampling window gets smaller, the number of times an asynchronous transition occurs during the sampling window drops. B.
C Instruction Set Descriptions
APPENDIX C INSTRUCTION SET DESCRIPTIONS This appendix provides reference information for the 80C186 Modular Core family instruction set. Tables C-1 through C-3 define the variables used in Table C-4, which lists the instructions with their descriptions and operations. Table C-1. Instruction Format Variables Variable Description dest A register or memory location that may contain data operated on by the instruction, and which receives (is replaced by) the result of the operation.
INSTRUCTION SET DESCRIPTIONS Table C-2. Instruction Operands Operand Description reg An 8- or 16-bit general register. reg16 An 16-bit general register. seg-reg A segment register. accum Register AX or AL immed A constant in the range 0–FFFFH. immed8 A constant in the range 0–FFH. mem An 8- or 16-bit memory location. mem16 A 16-bit memory location. mem32 A 32-bit memory location. src-table Name of 256-byte translate table. src-string Name of string addressed by register SI.
INSTRUCTION SET DESCRIPTIONS Table C-3. Flag Bit Functions Name AF Function Auxiliary Flag: Set on carry from or borrow to the low order four bits of AL; cleared otherwise. CF Carry Flag: Set on high-order bit carry or borrow; cleared otherwise. DF Direction Flag: Causes string instructions to auto decrement the appropriate index register when set. Clearing DF causes auto increment.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set Name AAA Description ASCII Adjust for Addition: AAA Changes the contents of register AL to a valid unpacked decimal number; the high-order half-byte is zeroed.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name AAS Description ASCII Adjust for Subtraction: AAS Corrects the result of a previous subtraction of two valid unpacked decimal operands (the destination operand must have been specified as register AL). Changes the content of AL to a valid unpacked decimal number; the high-order half-byte is zeroed.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name ADD Description Addition: Operation Flags Affected (dest) ← (dest) + (src) AF ü CF ü DF – IF – OF ü PF ü SF ü TF – ZF ü (dest) ← (dest) and (src) (CF) ← 0 (OF) ← 0 AF ? CF ü DF – IF – OF ü PF ü SF ü TF – ZF ü ADD dest, src Sums two operands, which may be bytes or words, replaces the destination operand. Both operands may be signed or unsigned binary numbers (see AAA and DAA).
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name BOUND Description Detect Value Out of Range: BOUND dest, src Provides array bounds checking in hardware. The calculated array index is placed in one of the general purpose registers, and the upper and lower bounds of the array are placed in two consecutive memory locations.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name CBW Description Convert Byte to Word: CBW Extends the sign of the byte in register AL throughout register AH. Use to produce a double-length (word) dividend from a byte prior to performing byte division.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name CLI Description Clear Interrupt-enable Flag: Operation Flags Affected (IF) ← 0 AF – CF – DF – IF ü OF – PF – SF – TF – ZF – if AF – CF ü DF – IF – OF – PF – SF – TF – ZF – CLI Zeroes the interrupt-enable flag (IF). When the interrupt-enable flag is cleared, the 8086 and 8088 do not recognize an external interrupt request that appears on the INTR line; in other words maskable interrupts are disabled.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name CMP Description Compare: Operation (dest) – (src) CMP dest, src Subtracts the source from the destination, which may be bytes or words, but does not return the result. The operands are unchanged, but the flags are updated and can be tested by a subsequent conditional jump instruction. The comparison reflected in the flags is that of the destination to the source.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name CWD Description Convert Word to Doubleword: CWD Extends the sign of the word in register AX throughout register DX. Use to produce a double-length (doubleword) dividend from a word prior to performing word division.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name DEC Description Decrement: Operation (dest) ← (dest) – 1 DEC dest Subtracts one from the destination operand. The operand may be a byte or a word and is treated as an unsigned binary number (see AAA and DAA).
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name DIV Description Divide: DIV src Performs an unsigned division of the accumulator (and its extension) by the source operand. If the source operand is a byte, it is divided into the two-byte dividend assumed to be in registers AL and AH. The byte quotient is returned in AL, and the byte remainder is returned in AH. If the source operand is a word, it is divided into the two-word dividend in registers AX and DX.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name ENTER Description Procedure Entry: ENTER locals, levels Executes the calling sequence for a high-level language. It saves the current frame pointer in BP, copies the frame pointers from procedures below the current call (to allow access to local variables in these procedures) and allocates space on the stack for the local variables of the current procedure invocation.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name HLT Description Halt: Operation None HLT Causes the CPU to enter the halt state. The processor leaves the halt state upon activation of the RESET line, upon receipt of a non-maskable interrupt request on NMI, or upon receipt of a maskable interrupt request on INTR (if interrupts are enabled).
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name IDIV Description Integer Divide: IDIV src Performs a signed division of the accumulator (and its extension) by the source operand. If the source operand is a byte, it is divided into the doublelength dividend assumed to be in registers AL and AH; the single-length quotient is returned in AL, and the single-length remainder is returned in AH.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name IMUL Description Integer Multiply: IMUL src Performs a signed multiplication of the source operand and the accumulator. If the source is a byte, then it is multiplied by register AL, and the double-length result is returned in AH and AL. If the source is a word, then it is multiplied by register AX, and the double-length result is returned in registers DX and AX.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name INC Description Increment: Operation (dest) ← (dest) + 1 AF ü CF – DF – IF – OF ü PF ü SF ü TF – ZF ü (dest) ← (src) AF – CF – DF – IF – OF – PF – SF – TF – ZF – INC dest Adds one to the destination operand. The operand may be byte or a word and is treated as an unsigned binary number (see AAA and DAA). Instruction Operands: INC reg INC mem INS In String: INS dest-string, port Performs block input from an I/O port to memory.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name INT Description Interrupt: INT interrupt-type Activates the interrupt procedure specified by the interrupt-type operand. Decrements the stack pointer by two, pushes the flags onto the stack, and clears the trap (TF) and interrupt-enable (IF) flags to disable single-step and maskable interrupts. The flags are stored in the format used by the PUSHF instruction.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name INTO Description Interrupt on Overflow: INTO Generates a software interrupt if the overflow flag (OF) is set; otherwise control proceeds to the following instruction without activating an interrupt procedure. INTO addresses the target interrupt procedure (its type is 4) through the interrupt pointer at location 10H; it clears the TF and IF flags and otherwise operates like INT.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name JAE JNB Description Jump on Above or Equal: Jump on Not Below: JAE disp8 JNB disp8 Operation if (CF) = 0 then (IP) ← (IP) + disp8 (sign-ext to 16 bits) Transfers control to the target location if the tested condition (CF = 0) is true.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name JCXZ Description Jump if CX Zero: JCXZ disp8 Transfers control to the target location if CX is 0. Useful at the beginning of a loop to bypass the loop if CX has a zero value, i.e., to execute the loop zero times.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name JL JNGE Description Jump on Less Than: Jump on Not Greater Than or Equal: JL disp8 JNGE disp8 Operation if AF – CF – DF – IF – OF – PF – SF – TF – ZF – if AF – CF – DF – IF – OF – PF – SF – TF – ZF – if AF – CF – DF – IF – OF – PF – SF – TF – ZF – (SF) ≠ (OF) then (IP) ← (IP) + disp8 (sign-ext to 16 bits) Transfers control to the target location if the condition tested (SF≠OF) is true.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name JNE JNZ Description Jump on Not Equal: Jump on Not Zero: JNE disp8 JNZ disp8 Operation if (ZF) = 0 then (IP) ← (IP) + disp8 (sign-ext to 16 bits) Transfers control to the target location if the tested condition (ZF = 0) is true. Instruction Operands: JNE short-label JNZ short-label JNO Jump on Not Overflow: JNO disp8 Transfers control to the target location if the tested condition (OF = 0) is true.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name JO Description Jump on Overflow: JO disp8 Transfers control to the target location if the tested condition (OF = 1) is true.
INSTRUCTION SET DESCRIPTIONS Table C-4.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name LES Description Load Pointer Using ES: LES dest, src Operation Flags Affected (dest) ← (EA) (ES) ← (EA + 2) AF – CF – DF – IF – OF – PF – SF – TF – ZF – none AF – CF – DF – IF – OF – PF – SF – TF – ZF – Transfers a 32-bit pointer variable from the source operand to the destination operand and register ES. The offset word of the pointer is transferred to the destination operand.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name LODS Description Load String (Byte or Word): LODS src-string Transfers the byte or word string element addressed by SI to register AL or AX and updates SI to point to the next element in the string. This instruction is not ordinarily repeated since the accumulator would be overwritten by each repetition, and only the last element would be retained.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name Description LOOPNE LOOPNZ Loop While Not Equal: Loop While Not Zero: LOOPNE disp8 LOOPNZ disp8 Decrements CX by 1 and transfers control to the target location if CX is not 0 and if ZF is clear; otherwise the next sequential instruction is executed.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name MOVS Description Move String: Operation Flags Affected (dest-string) ← (src-string) AF – CF – DF – IF – OF – PF – SF – TF – ZF – When Source Operand is a Byte: AF ? CF ü DF – IF – OF ü PF ? SF ? TF – ZF ? MOVS dest-string, src-string Transfers a byte or a word from the source string (addressed by SI) to the destination string (addressed by DI) and updates SI and DI to point to the next string element.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name NEG Description Negate: NEG dest Subtracts the destination operand, which may be a byte or a word, from 0 and returns the result to the destination. This forms the two's complement of the number, effectively reversing the sign of an integer. If the operand is zero, its sign is not changed. Attempting to negate a byte containing –128 or a word containing – 32,768 causes no change to the operand and sets OF.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name OR Description Logical OR: OR dest,src Performs the logical "inclusive or" of the two operands (bytes or words) and returns the result to the destination operand. A bit in the result is set if either or both corresponding bits in the original operands are set; otherwise the result bit is cleared.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name OUTS Description Out String: Operation Flags Affected (dst) ← (src) AF – CF – DF – IF – OF – PF – SF – TF – ZF – (dest) ← ((SP) + 1:(SP)) (SP) ← (SP) + 2 AF – CF – DF – IF – OF – PF – SF – TF – ZF – OUTS port, src_string Performs block output from memory to an I/O port. The port address is placed in the DX register. The memory address is placed in the SI register.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name POPA Description Pop All: POPA Pops all data, pointer, and index registers off of the stack. The SP value popped is discarded.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name PUSHA Description Push All: PUSHA Pushes all data, pointer, and index registers onto the stack . The order in which the registers are saved is: AX, CX, DX, BX, SP, BP, SI, and DI. The SP value pushed is the SP value before the first register (AX) is pushed.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name RCL Description Rotate Through Carry Left: RCL dest, count Rotates the bits in the byte or word destination operand to the left by the number of bits specified in the count operand. The carry flag (CF) is treated as "part of" the destination operand; that is, its value is rotated into the loworder bit of the destination, and itself is replaced by the high-order bit of the destination.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name Description REP REPE REPZ REPNE REPNZ Repeat: Repeat While Equal: Repeat While Zero: Repeat While Not Equal: Repeat While Not Zero: Controls subsequent string instruction repetition. The different mnemonics are provided to improve program clarity. REP is used in conjunction with the MOVS (Move String) and STOS (Store String) instructions and is interpreted as "repeat while not end-of-string" (CX not 0).
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name RET Description Return: RET optional-pop-value Transfers control from a procedure back to the instruction following the CALL that activated the procedure. The assembler generates an intrasegment RET if the programmer has defined the procedure near, or an intersegment RET if the procedure has been defined as far.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name ROR Description Rotate Right: ROR dest, count Operates similar to ROL except that the bits in the destination byte or word are rotated right instead of left.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name SHL SAL Description Shift Logical Left: Shift Arithmetic Left: SHL dest, count SAL dest, count Shifts the destination byte or word left by the number of bits specified in the count operand. Zeros are shifted in on the right. If the sign bit retains its original value, then OF is cleared.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name SBB Description Subtract With Borrow: SBB dest, src Subtracts the source from the destination, subtracts one if CF is set, and returns the result to the destination operand. Both operands may be bytes or words.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name SCAS Description Scan String: SCAS dest-string Subtracts the destination string element (byte or word) addressed by DI from the content of AL (byte string) or AX (word string) and updates the flags, but does not alter the destination string or the accumulator. SCAS also updates DI to point to the next string element and AF, CF, OF, PF, SF and ZF to reflect the relationship of the scan value in AL/AX to the string element.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name SHR Description Shift Logical Right: SHR dest, src Shifts the bits in the destination operand (byte or word) to the right by the number of bits specified in the count operand. Zeros are shifted in on the left. If the sign bit retains its original value, then OF is cleared.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name STI Description Set Interrupt-enable Flag: Operation Flags Affected (IF) ← 1 AF – CF – DF – IF ü OF – PF – SF – TF – ZF – When Source Operand is a Byte: AF – CF – DF – IF – OF – PF – SF – TF – ZF – STI Sets IF to 1, enabling processor recognition of maskable interrupt requests appearing on the INTR line. Note however, that a pending interrupt will not actually be recognized until the instruction following STI has executed.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name SUB Description Subtract: Operation Flags Affected (dest) ← (dest) – (src) AF ü CF ü DF – IF – OF ü PF ü SF ü TF – ZF ü (dest) and (src) (CF ) ← 0 (OF) ← 0 AF ? CF ü DF – IF – OF ü PF ü SF ü TF – ZF ü SUB dest, src The source operand is subtracted from the destination operand, and the result replaces the destination operand. The operands may be bytes or words.
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name WAIT Description Wait: Operation None AF – CF – DF – IF – OF – PF – SF – TF – ZF – (temp) ← (dest) (dest) ← (src) (src) ← (temp) AF – CF – DF – IF – OF – PF – SF – TF – ZF – WAIT Causes the CPU to enter the wait state while its test line is not active. Instruction Operands: none XCHG Exchange: XCHG dest, src Switches the contents of the source and destination operands (bytes or words).
INSTRUCTION SET DESCRIPTIONS Table C-4. Instruction Set (Continued) Name XLAT Description Translate: Operation Flags Affected AL ← ((BX) + (AL)) AF – CF – DF – IF – OF – PF – SF – TF – ZF – (dest) ← (dest) xor (src) (CF) ← 0 (OF) ← 0 AF ? CF ü DF – IF – OF ü PF ü SF ü TF – ZF ü XLAT translate-table Replaces a byte in the AL register with a byte from a 256-byte, user-coded translation table. Register BX is assumed to point to the beginning of the table.
D Instruction Set Opcodes and Clock Cycles
APPENDIX D INSTRUCTION SET OPCODES AND CLOCK CYCLES This appendix provides reference information for the 80C186 Modular Core family instruction set. Table D-1 defines the variables used in Table D-2, which lists the instructions with their formats and execution times. Table D-3 is a guide for decoding machine instructions. Table D-4 is a guide for encoding instruction mnemonics, and Table D-5 defines Table D-4 abbreviations. Table D-1.
INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2.
INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2.
INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2.
INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2.
INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2.
INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2.
INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2.
INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-2.
INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-3.
INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-3.
INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-3.
INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-3.
INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-3.
INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-3.
INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-3.
INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-3.
INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-3.
INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-3.
INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-4.
INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-4.
INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-5.
Index
INDEX 80C187 Math Coprocessor, 10-2–10-8 accessing, 10-10–10-11 arithmetic instructions, 10-3–10-4 bus cycles, 10-11 clocking, 10-10 code examples, 10-13–10-16 comparison instructions, 10-5 constant instructions, 10-6 data transfer instructions, 10-3 data types, 10-7–10-8 design considerations, 10-10–10-11 example floating point routine, 10-16 exceptions, 10-13 I/O port assignments, 10-10 initialization example, 10-13–10-16 instruction set, 10-2 interface, 10-7–10-13 and chip-selects, 6-17, 10-11 and PCB lo
INDEX and chip-selects, 6-5 HALT state, exiting, 3-30 idle states, 3-18 instruction prefetch, 3-20 interrupt acknowledge (INTA) cycles, 3-6, 3-25–3-26, 8-9 and chip-selects, 6-5 interrupt acknowledge cycles, 8-29 operation, 3-7–3-20 priorities, 3-44–3-45, 7-2 read cycles, 3-20–3-21 refresh cycles, 3-22, 7-4, 7-5 control signals, 7-5, 7-6 during HOLD, 3-41–3-43, 7-12–7-13 wait states, 3-13–3-18 write cycles, 3-22–3-25 See also Data transfers Bus hold protocol, 3-39–3-44 and CLKOUT, 5-6 and CSU, 6-18 and ref
INDEX Data sheets, obtaining from BBS, 1-5 Data transfers, 3-1–3-6 instructions, 2-18 PCB considerations, 4-5 PSW flag storage formats, 2-19 See also Bus cycles Data types, 2-37–2-38 DI register, 2-1, 2-5, 2-13, 2-22, 2-23, 2-30, 2-32, 2-34 Digital one-shot, code example, 9-17–9-23 Direct Memory Access (DMA) Unit, 10-1–10-27 and BIU, 10-8 and CSU, 10-8 and PCB, 10-3 arming channel, 10-18 DMA acknowledge signal, 10-2, 10-22 DRQ timing, 10-20 examples, 10-22–10-27 HALT bit, 8-22, 8-23, 10-20 hardware conside
INDEX F Fault exceptions, 2-43 FaxBack service, 1-4 F-Bus and PCB, 4-5 operation, 4-5 Flags‚ See Processor Status Word (PSW) Floating Point, defined, 2-37 H HALT bus cycle‚ See Bus cycles HOLD/HLDA protocol‚ See Bus hold protocol Hypertext manuals, obtaining from BBS, 1-5 I I/O devices interfacing with, 3-6–3-7 memory-mapped, 3-6 I/O ports addressing, 2-36 I/O space, 3-1–3-7 accessing, 3-6 reserved locations, 2-15, 6-17 Idle states and bus cycles, 3-18 Immediate operands, 2-28 IMUL instruction, A-9 Input
INDEX maskable, 2-43 masking, 8-3, 8-12, 8-16 priority-based, 8-17 multiplexed, 8-7 nesting, 8-4 NMI, 2-42 nonmaskable, 2-45 overview, 8-1, 8-2 priority, 2-46–2-49, 8-3 default, 8-3 resolution, 8-5, 8-6 processing, 2-39–2-42 reserved, 2-39 response time, 2-46 selecting edge- or level-triggering, 8-12 slave mode sources, 8-25 software, 2-45 timer interrupts, 9-16 types, 8-9, 8-26, 8-27 See also Exceptions, Interrupt Control Unit INTn instruction, 2-45 Invalid opcode trap (Type 6 exception), 2-44 IRET instru
INDEX Polling, 8-1, 8-9 POPA instruction, A-1 Power consumption‚ reducing, 3-28 Power management, 5-10–5-14 Power management modes and HALT bus cycles, 3-30 Powerdown mode, 7-2 Power-Save mode, 5-11–5-14, 7-2 and DRAM refresh rate, 5-13 and refresh interval, 7-7 control register, 5-12 entering, 5-11 exiting, 5-13 initialization code, 5-13–5-14 Power-Save Register, 5-12 Priority Mask register, 8-17, 8-18, 8-28 Processor control instructions, 2-27 Processor Status Word (PSW), 2-1, 2-7, 2-41 bits defined, 2-7
INDEX SI register, 2-1, 2-5, 2-13, 2-22, 2-23, 2-30, 2-32, 2-34 Sign Flag (SF), 2-7, 2-9 Single-step trap (Type 1 exception), 2-43 Software code example 80C187 floating-point routine, 10-16 80C187 initialization, 10-13–10-15 digital one-shot, 9-17–9-23 DMA initialization, 10-22–10-27 ICU initialization, 8-31 real-time clock, 9-17–9-19 square-wave generator, 9-17–9-22 TCU configurations, 9-17–9-23 timed DMA transfers, 10-22–10-27 data types, 2-37, 2-38 dynamic code relocation, 2-13, 2-14 interrupts, 2-45 ov
INDEX and PCB accesses, 4-4 and READY input, 3-13 Word integer, defined, 10-7 World Wide Web, 1-6 Write bus cycle, 3-22 Z Zero Flag (ZF), 2-7, 2-9, 2-23 Index-8
