16-Bit High-Integration Embedded Processors Specification Sheet

80C186EA/80C188EA, 80L186EA/80L188EA
PCB
Function
Offset
00H Reserved
02H Reserved
04H Reserved
06H Reserved
08H Reserved
0AH Reserved
0CH Reserved
0EH Reserved
10H Reserved
12H Reserved
14H Reserved
16H Reserved
18H Reserved
1AH Reserved
1CH Reserved
1EH Reserved
20H Reserved
22H End of Interrupt
24H Poll
26H Poll Status
28H Interrupt Mask
2AH Priority Mask
2CH In-Service
2EH Interrupt Request
30H Interrupt Status
32H Timer Control
34H DMA0 Int. Control
36H DMA1 Int. Control
38H INT0 Control
3AH INT1 Control
3CH INT2 Control
3EH INT3 Control
PCB
Function
Offset
40H Reserved
42H Reserved
44H Reserved
46H Reserved
48H Reserved
4AH Reserved
4CH Reserved
4EH Reserved
50H Timer 0 Count
52H Timer 0 Compare A
54H Timer 0 Compare B
56H Timer 0 Control
58H Timer 1 Count
5AH Timer 1 Compare A
5CH Timer 1 Compare B
5EH Timer 1 Control
60H Timer 2 Count
62H Timer 2 Compare
64H Reserved
66H Timer 2 Control
68H Reserved
6AH Reserved
6CH Reserved
6EH Reserved
70H Reserved
72H Reserved
74H Reserved
76H Reserved
78H Reserved
7AH Reserved
7CH Reserved
7EH Reserved
PCB
Function
Offset
80H Reserved
82H Reserved
84H Reserved
86H Reserved
88H Reserved
8AH Reserved
8CH Reserved
8EH Reserved
90H Reserved
92H Reserved
94H Reserved
96H Reserved
98H Reserved
9AH Reserved
9CH Reserved
9EH Reserved
A0H UMCS
A2H LMCS
A4H PACS
A6H MMCS
A8H MPCS
AAH Reserved
ACH Reserved
AEH Reserved
B0H Reserved
B2H Reserved
B4H Reserved
B6H Reserved
B8H Reserved
BAH Reserved
BCH Reserved
BEH Reserved
PCB
Function
Offset
C0H DMA0 Src. Lo
C2H DMA0 Src. Hi
C4H DMA0 Dest. Lo
C6H DMA0 Dest. Hi
C8H DMA0 Count
CAH DMA0 Control
CCH Reserved
CEH Reserved
D0H DMA1 Src. Lo
D2H DMA1 Src. Hi
D4H DMA1 Dest. Lo
D6H DMA1 Dest. Hi
D8H DMA1 Count
DAH DMA1 Control
DCH Reserved
DEH Reserved
E0H Refresh Base
E2H Refresh Time
E4H Refresh Control
E6H Reserved
E8H Reserved
EAH Reserved
ECH Reserved
EEH Reserved
F0H Power-Save
F2H Power Control
F4H Reserved
F6H Step ID
F8H Reserved
FAH Reserved
FCH Reserved
FEH Relocation
Figure 3. Peripheral Control Block Registers
6
6