16-Bit High-Integration Embedded Processors Specification Sheet

80C186EA/80C188EA, 80L186EA/80L188EA
INSTRUCTION SET SUMMARY (Continued)
Function Format
80C186EA 80C188EA
Comments
Clock Clock
Cycles Cycles
ARITHMETIC (Continued)
IMUL
e
Integer multiply (signed): 1111011w mod101 r/m
Register-Byte 25–28 25–28
Register-Word 34–37 34–37
Memory-Byte 31–34 32–34
Memory-Word 40–43 40–43*
IMUL
e
Integer Immediate multiply 011010s1 modreg r/m data data if s
e
0 22–25 22-25
(signed)
29–32 29–32
DIV
e
Divide (unsigned): 1111011w mod110 r/m
Register-Byte 29 29
Register-Word 38 38
Memory-Byte 35 35
Memory-Word 44 44
*
IDIV
e
Integer divide (signed): 1111011w mod111 r/m
Register-Byte 44–52 44–52
Register-Word 53–61 53–61
Memory-Byte 50–58 50–58
Memory-Word 59–67 59–67*
AAM
e
ASCII adjust for multiply 11010100 00001010 19 19
AAD
e
ASCII adjust for divide 11010101 00001010 15 15
CBW
e
Convert byte to word 10011000 2 2
CWD
e
Convert word to double word 10011001 4 4
LOGIC
Shift/Rotate Instructions:
Register/Memory by 1 1101000w modTTTr/m 2/15 2/15
Register/Memory by CL 1101001w modTTTr/m 5
a
n/17
a
n5
a
n/17
a
n
Register/Memory by Count 1100000w modTTTr/m count 5
a
n/17
a
n5
a
n/17
a
n
TTT Instruction
000 ROL
001 ROR
010 RCL
011 RCR
1 0 0 SHL/SAL
101 SHR
111 SAR
AND
e
And:
Reg/memory and register to either 001000dw modreg r/m 3/10 3/10*
Immediate to register/memory 1000000w mod100 r/m data data if w
e
1 4/16 4/16*
Immediate to accumulator 0010010w data data if w
e
1 3/4 3/4* 8/16-bit
TEST
e
And function to flags, no result:
Register/memory and register 1000010w modreg r/m 3/10 3/10
*
Immediate data and register/memory 1111011w mod000 r/m data data if w
e
1 4/10 4/10*
Immediate data and accumulator 1010100w data data if w
e
1 3/4 3/4 8/16-bit
OR
e
Or:
Reg/memory and register to either 000010dw modreg r/m 3/10 3/10*
Immediate to register/memory 1000000w mod001 r/m data data if w
e
1 4/16 4/16
*
Immediate to accumulator 0000110w data data if w
e
1 3/4 3/4* 8/16-bit
Shaded areas indicate instructions not available in 8086/8088 microsystems.
NOTE:
*Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.
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