16-Bit High-Integration Embedded Processors Specification Sheet
80C186EA/80C188EA, 80L186EA/80L188EA
I
CC
VERSUS FREQUENCY AND VOLTAGE
The current (I
CC
) consumption of the processor is
essentially composed of two components; I
PD
and
I
CCS
.
I
PD
is the quiescent current that represents internal
device leakage, and is measured with all inputs or
floating outputs at GND or V
CC
(no clock applied to
the device). I
PD
is equal to the Powerdown current
and is typically less than 50 mA.
I
CCS
is the switching current used to charge and
discharge parasitic device capacitance when chang-
ing logic levels. Since I
CCS
is typically much greater
than I
PD
,I
PD
can often be ignored when calculating
I
CC
.
I
CCS
is related to the voltage and frequency at which
the device is operating. It is given by the formula:
Power
e
V
c
I
e
V
2
c
C
DEV
c
f
.
.
. I
e
I
CC
e
I
CCS
e
V
c
C
DEV
c
f
Where: V
e
Device operating voltage (V
CC
)
C
DEV
e
Device capacitance
f
e
Device operating frequency
I
CCS
e
I
CC
e
Device current
Measuring C
DEV
on a device like the 80C186EA
would be difficult. Instead, C
DEV
is calculated using
the above formula by measuring I
CC
at a known V
CC
and frequency (see Table 11). Using this C
DEV
val-
ue, I
CC
can be calculated at any voltage and fre-
quency within the specified operating range.
EXAMPLE: Calculate the typical I
CC
when operating
at 20 MHz, 4.8V.
I
CC
e
I
CCS
e
4.8
c
0.515
c
20
&
49 mA
PDTMR PIN DELAY CALCULATION
The PDTMR pin provides a delay between the as-
sertion of NMI and the enabling of the internal
clocks when exiting Powerdown. A delay is required
only when using the on-chip oscillator to allow the
crystal or resonator circuit time to stabilize.
NOTE:
The PDTMR pin function does not apply when
RESIN
is asserted (i.e., a device reset during Pow-
erdown is similar to a cold reset and RESIN
must
remain active until after the oscillator has stabi-
lized).
To calculate the value of capacitor required to pro-
vide a desired delay, use the equation:
440
c
t
e
C
PD
(5V, 25
§
C)
Where: t
e
desired delay in seconds
C
PD
e
capacitive load on PDTMR in mi-
crofarads
EXAMPLE: To get a delay of 300 ms, a capacitor
value of C
PD
e
440
c
(300
c
10
b
6
)
e
0.132 mFis
required. Round up to standard (available) capaci-
tive values.
NOTE:
The above equation applies to delay times greater
than 10 ms and will compute the TYPICAL capaci-
tance needed to achieve the desired delay. A delay
variance of
a
50% or
b
25% can occur due to
temperature, voltage, and device process ex-
tremes. In general, higher V
CC
and/or lower tem-
perature will decrease delay time, while lower V
CC
and/or higher temperature will increase delay time.
Table 11. C
DEV
Values
Parameter Typ Max Units Notes
C
DEV
(Device in Reset) 0.515 0.905 mA/V*MHz 1, 2
C
DEV
(Device in Idle) 0.391 0.635 mA/V*MHz 1, 2
1. Max C
DEV
is calculated at
b
40
§
C, all floating outputs driven to V
CC
or GND, and all
outputs loaded to 50 pF (including CLKOUT and OSCOUT).
2. Typical C
DEV
is calculated at 25
§
C with all outputs loaded to 50 pF except CLKOUT and
OSCOUT, which are not loaded.
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