16-Bit High-Integration Embedded Processors Specification Sheet
80C186EA/80C188EA, 80L186EA/80L188EA
DC SPECIFICATIONS (80C186EA/80C188EA)
Symbol Parameter Min Max Units Conditions
V
CC
Supply Voltage 4.5 5.5 V
V
IL
Input Low Voltage for All Pins
b
0.5 0.3 V
CC
V
V
IH
Input High Voltage for All Pins 0.7 V
CC
V
CC
a
0.5 V
V
OL
Output Low Voltage 0.45 V I
OL
e
3 mA (min)
V
OH
Output High Voltage V
CC
b
0.5 V I
OH
eb
2 mA (min)
V
HYR
Input Hysterisis on RESIN 0.30 V
I
IL1
Input Leakage Current (except
g
10 mA0V
s
V
IN
s
V
CC
RD/QSMD, UCS, LCS, MCS0/PEREQ,
MCS1
/ERROR, LOCK and TEST/BUSY)
I
IL2
Input Leakage Current
b
275 mAV
IN
e
0.7 V
CC
(RD/QSMD, UCS, LCS, MCS0/PEREQ, (Note 1)
MCS1
, ERROR, LOCK and TEST/BUSY
I
OL
Output Leakage Current
g
10 mA
0.45
s
V
OUT
s
V
CC
(Note 2)
I
CC
Supply Current Cold (RESET)
80C186EA25/80C188EA25 105 mA (Notes 3, 5)
80C186EA20/80C188EA20 90 mA
80C186EA13/80C188EA13 65 mA
I
ID
Supply Current In Idle Mode
80C186EA25/80C188EA25 90 mA (Note 5)
80C186EA20/80C188EA20 70 mA
80C186EA13/80C188EA13 46 mA
I
PD
Supply Current In Powerdown Mode
80C186EA25/80C188EA25 100 mA (Note 5)
80C186EA20/80C188EA20 100 mA
80C186EA13/80C188EA13 100 mA
C
OUT
Output Pin Capacitance 0 15 pF T
F
e
1 MHz (Note 4)
C
IN
Input Pin Capacitance 0 15 pF T
F
e
1 MHz
NOTES:
1. RD
/QSMD, UCS, LCS, MCS0/PEREQ, MCS1/ERROR, LOCK and TEST/BUSY have internal pullups that are only acti-
vated during RESET. Loading these pins above I
OL
eb
275 mA will cause the processor to enter alternate modes of
operation.
2. Output pins are floated using HOLD or ONCE Mode.
3. Measured at worst case temperature and V
CC
with all outputs loaded as specified in the AC Test Conditions, and with the
device in RESET (RESIN
held low). RESET is worst case for I
CC
.
4. Output capacitance is the capacitive load of a floating output pin.
5. Operating conditions for 25 MHz are 0
§
Cto
a
70
§
C, V
CC
e
5.0V
g
10%.
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