32-Bit High-Performance Superscalar Processor Data Sheet

80960HA/HD/HT
66 Datasheet
Figure 41. Non-Burst, Pipelined Read Request without Wait States, 32-Bit Bus
ADS
A31:4, SUP,
CT3:0, D/C,
LOCK
BLAST
WAIT
D31:0,
CLKIN
IN
D
IN
D’
IN
D’’
IN
D’’’
IN
D’’’’
A
A’
D
A’’
D’
A’’’
D’’
A’’’’
D’’’
D’’’’
Valid Valid Valid Valid Valid Invalid
DT/R
DEN
A3:2
BE3:0
Valid Valid Valid Valid Valid Invalid
W/R
DP3:0
PCHK
1. Non-pipelined request concludes, pipelined reads begin.
2. Pipelined reads conclude, non-pipelined requests begin.
1
2
Burst
Bus
Width
Odd
Parity
N
XDA
N
WDD
N
WAD
N
RDD
29
28 2124 23-22 20 12-819-16 15-14 7-6 4-0
Disabled
0
ON
1
X
xxxx
32-Bit
X
x
Enabled
1
X
xx
X
xxxxx
X
xx
X
x
0
00000
Function
Bit
Value
External
Ready
Control
Pipe-
Lining Parity Enable
N
RAD
NOTE: Bits 31-30, 27-25, 13, and 5 are reserved.
10
Invalid
PMCON