32-Bit High-Performance Superscalar Processor Data Sheet

80960HA/HD/HT
Datasheet 55
Figure 30. Warm Reset Waveform
Maximum RESET Low to RESET State
16 CLKIN Periods
1 CLKIN
CLKIN
ADS
,
DT/R
SUP,
D31:0,
STEST
RESET
LOCK, WAIT,
DEN
, BLAST,
A31:2,
D/C
, BE3:0
DP3:0
Valid
Thold
Tsetup
1 CLKIN
W/R, BREQ, FAIL,
BSTALL
Minimum RESET Low Time
16 CLKIN Periods
RESET High to First Bus Activity,
HA=67, HD=34, HT=23
CLKIN Periods