32-Bit High-Performance Superscalar Processor Data Sheet

80960HA/HD/HT
Datasheet 45
4.7.1 A.C. Test Conditions
A.C. values are derived using the 50 pF load shown in Figure 8. Figure 25, “Output Delay or Hold vs.
Load Capacitance” on page 52
, shows how timings vary with load capacitance. Input waveforms
(except for CLKIN) are assumed to have a rise and fall time of ≤ 2ns from 0.8V to 2.0V.
Figure 8. A.C. Test Load
Output Pin
C
L
= 50 pF for all signals
C
L