32-Bit High-Performance Superscalar Processor Data Sheet

80960HA/HD/HT
72 Datasheet
Figure 47. Using External READY
CLKIN
ADS
A31:4, SUP,
DT/R
DEN
READY
W/R
CT3:0, D/C,
BLAST
BTERM
A3:2
WAIT
D31:0,
BE3:0, LOCK
D0 D1 D2 D3 D0 D1 D2 D3
00 01 10 11 00 01 10 11
ValidValid
Quad-Word Read Request
N
RAD
= 0, N
RDD
= 0, N
XDA
= 0
Ready Enabled
Quad-Word Write Request
N
WAD
= 1, N
WDD
= 0, N
WDA
= 0
Ready Enabled
DP3:0
PCHK
A 1 D D D D1A 2D1 D1 D1D
NOTE: Pipelining must be disabled to use READY
.