16-Bit HMOS Microprocessor Specification Sheet

8086

WAVEFORMS (Continued)

ASYNCHRONOUS SIGNAL RECOGNITION

231455–17

NOTE:

1. Setup requirements for asynchronous signals only to guarantee recognition at next CLK.

BUS LOCK SIGNAL TIMING (MAXIMUM MODE

ONLY)

231455–18

RESET TIMING

231455–19

REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY)

231455–20

NOTE:

The coprocessor may not drive the buses outside the region shown without risking contention.