Datasheet

ELECTRICAL SPECIFICATIONS
31
BCLK
RESET#
Configuration
(A20M#, IGNNE#,
LINT[1:0])
Configuration
(A[14:5]#, BR0#,
FLUSH#, INIT#)
P6CB 764
T
t
T9 (GTL+ Input Hold Time)=
T
u
T8 (GTL+ Input Setup Time)=
T
v
T10 (RESET# Pulse Width)
=
T
w
T16 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time)
=
T
x
T17 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time)
=
T20 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time)
T
y
=
T19 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Delay Time)
T
z
=
T18 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Setup Time)
T
y
T
z
T
v
T
x
T
t
T
u
T
w
Valid
Valid
Safe
Figure 7. System Bus Reset and Configuration Timings
BCLK
PWRGOOD
RESET#
Configuration
(A20M#, IGNNE#,
LINT[1:0])
000765b
T
a
T
b
T
c
T
a
T15 (PWRGOOD Inactive Pulse Width)=
T
b
T10 (RESET# Pulse Width)=
T
c
T20 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time)=
Valid Ratio
V
TT
V
CORE
CC
V
CC
2.5
Figure 8. Power-On Reset and Configuration Timings