Datasheet

TABLE OF CONTENTS
2
TABLE OF CONTENTS
PRODUCT FEATURES............................................................................................................ I
1. INTRODUCTION .........................................................................................................................6
2. TERMINOLOGY .......................................................................................................................... 7
2.1 S.E.C. CARTRIDGE TERMINOLOGY....................................................................................7
2.2 STATE OF DATA ................................................................................................................ 8
2.3 REFERENCES....................................................................................................................8
3. ELECTRICAL SPECIFICATIONS............................................................................................... 9
3.1 SYSTEM BUS AND VREF................................................................................................... 9
3.2 POWER AND GROUND PINS ............................................................................................... 9
3.3 DECOUPLING GUIDELINES ...............................................................................................11
3.3.1 VCC_CORE ...................................................................................................................11
3.3.2 LEVEL 2 CACHE DECOUPLING............................................................................. 11
3.3.3 SYSTEM BUS AGTL+ DECOUPLING..................................................................... 11
3.4 CLOCK FREQUENCIES AND SYSTEM BUS CLOCK RATIOS ..................................................11
3.4.2 MIXING PROCESSORS OF DIFFERENT FREQUENCIES ................................... 13
3.5 VOLTAGE IDENTIFICATION................................................................................................ 13
3.6 SYSTEM BUS UNUSED PINS AND TEST PINS..................................................................... 16
3.7 SYSTEM BUS SIGNAL GROUPS ........................................................................................ 16
3.7.2 ASYNCHRONOUS VS. SYNCHRONOUS FOR SYSTEM BUS SIGNALS ............ 17
3.8 ACCESS PORT (TAP) CONNECTION.................................................................................17
3.9 MAXIMUM RATINGS .........................................................................................................18
3.10 PROCESSOR DC SPECIFICATIONS ................................................................................... 18
3.11 AGTL+ SYSTEM BUS SPECIFICATIONS ............................................................................22
3.12 SYSTEM BUS AC SPECIFICATIONS................................................................................... 24
4. SIGNAL QUALITY.....................................................................................................................33
4.1 BUS CLOCK SIGNAL QUALITY SPECIFICATIONS ......................................................................... 33
4.2 AGTL+ SIGNAL QUALITY SPECIFICATIONS....................................................................... 34
4.2.2 AGTL+ Signal Quality Specifications ..............................................................................34
4.2.3 AGTL+ OVERSHOOT/UNDERSHOOT GUIDELINES ............................................ 34
4.3 NON-GTL+ SIGNAL QUALITY SPECIFICATIONS.......................................................................... 37
4.3.1 2.5V Signal Overshoot/Undershoot Guidelines ............................................................. 38
4.3.2 BCLK Overshoot/Undershoot Guidelines and Specifications........................................39
4.3.3 Measuring BCLK Overshoot/Undershoot........................................................................ 39
4.3.4 2.5V TOLERANT BUFFER RINGBACK SPECIFICATION ............................................40
4.3.5 2.5V TOLERANT BUFFER SETTLING LIMIT GUIDELINE............................................ 40
5. PROCESSOR FEATURES........................................................................................................ 41
5.1 LOW POWER STATES AND CLOCK CONTROL............................................................................. 41
5.1.1 NORMAL STATE — STATE 1................................................................................. 41
5.1.2 AUTO HALT POWER DOWN STATE — STATE 2................................................. 41