Datasheet

ELECTRICAL SPECIFICATIONS
28
Table 18. System Bus AC Specifications (TAP Connection) at the processor Core
1
T# Parameter Min Max Unit Figure Notes
T30: TCK Frequency 16.667 MHz
T31: TCK Period 60.0 nS Figure 3
T32: TCK High Time 25.0 nS Figure 3 @1.7V 2
T33: TCK Low Time 25.0 nS Figure 3 @0.7V 2
T34: TCK Rise Time 5.0 nS Figure 3 (0.7V–1.7V) 2, 3
T35: TCK Fall Time 5.0 nS Figure 3 (1.7V–0.7V) 2, 3
T36: TRST# Pulse Width 40.0 nS Figure 10 (Asynchronous) 2
T37: TDI, TMS Setup Time 5.0 nS Figure 9 4
T38: TDI, TMS Hold Time 14.0 nS Figure 9 4
T39: TDO Valid Delay 1.0 10.0 nS Figure 9 5, 6
T40: TDO Float Delay 25.0 nS Figure 9 2, 5, 6
T41: All Non-Test Outputs Valid
Delay
2.0 25.0 nS Figure 9 5, 7, 8
T42: All Non-Test Inputs Setup
Time
25.0 nS Figure 9 2, 5, 7, 8
T43: All Non-Test Inputs Setup
Time
5.0 nS Figure 9 4, 7, 8
T44: All Non-Test Inputs Hold
Time
13.0 nS Figure 9 4, 7, 8
NOTES:
1. Unless otherwise noted, these specifications are tested during manufacturing.
2. Not 100% tested. Specified by design characterization.
3. 1 nS can be added to the maximum TCK rise and fall times for every 1 MHz below 16.667 MHz.
4. Referenced to TCK rising edge.
5. Referenced to TCK falling edge.
6. Valid delay timing for this signal is specified to 2.5V.
7. Non-Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO and TMS). These timings
correspond to the response of these signals due to TAP operations.
8. During Debug Port operation, use the normal specified timings rather than the TAP signal timings.