Datasheet

ELECTRICAL SPECIFICATIONS
20
Table 6. Current Specifications
1,10
Symbol Parameter Min Typ Max Unit Notes
Icc_core
@ 2.74V VCC_CORE
700 MHz
900 MHz
13.9
17.0
A 2
Icc_core
@ 4.75V VCC_CORE
700 MHz
900 MHz
8.4
10.3
A 2
Icc_core
@ 11.4V VCC_CORE
700 MHz
900 MHz
3.5
4.3
A 2
Icc_core FMB 2.74V
4.75V
11.4V
19.0
11.0
5.0
A 1, 2, 10
IV
TT
Termination voltage
supply current
0 0.3 1.2 A 4
I
SGnt
I
CC
Stop Grant for
processor core
2.8V
5.0V
12.0V
- - 10.0
5.6
2.3
A
3,5
I
CC
SLP
I
CC
Sleep for processor
core
2.8V
5.0V
12.0V
-
-
10.0
5.6
2.3
A
3
DlccCORE/dt Current slew rate 10 A/µs 6,7
Dl
CCV
TT
/dt Termination current slew
rate
5 A/µs 7
I
CC
TAP
I
CC
for TAP power
supply
100 mA
I
CC
SMBus
I
CC
for SMBus power
supply
3 22.5 mA 8
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes. “FMB” is a suggested
design guideline for flexible motherboard design.
2. Vcc_core/Icc_core supplies the processor core, integrated L2 cache and OCVR.
3. Max I
CC
measurements are measured at V
CC
minimum voltage (at VRM or system power supply output) under maximum signal
loading conditions.
4. This is the current required for a single processor. A similar current is drawn through the termination resistors of each load on the
AGTL+ bus. V
TT
is decoupled on the SC330 cartridge such that negative current flow due to the active pull-up to VCC_
CORE
in the
processor will not be seen at the processor fingers.
5. The current specified is also for AutoHALT state.
6. Maximum values are specified by design/characterization at nominal V
CC
and at the SC330 edge fingers.
7. Based on simulation and averaged over the duration of any change in current. Use to compute the maximum inductance tolerable
and reaction time of the voltage regulator. This parameter is not tested.