Datasheet
ELECTRICAL SPECIFICATIONS
17
Table 3. Processor pin Groups
Group Name Signals
AGTL+ Input BPRI#, BR[3:1]#
1
, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY#
AGTL+ Output PRDY#
AGTL+ I/O A[35:03]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#,
BR0#
1
, D[63:00]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#, LOCK#,
REQ[4:0]#, RP#
CMOS Input A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, PWRGD
2
,
SMI#, SLP#
2
, STPCLK#
CMOS Output FERR#, IERR#, THERMTRIP#
2
System Bus Clock BCLK
APIC Clock PICCLK
APIC I/O
3
PICD[1:0]
TAP Input
3
TCK, TDI, TMS, TRST#
TAP Output
3
TDO
SMBus Interface SMBDAT, SMBCLK, SMBALERT#, WP
Power/Other
4
VCC_
CORE
, Vcc_
TAP
, Vcc_
SMB,
V
TT
, V
SS
, RESERVED_XXX, SA[2:1],
SELFSB[0:1], OCVR_EN, OCVR_OK, VIN_SENSE, CORE_AN_VSENSE,
HV_EN#
NOTES:
1. The BR0# pin is the only BREQ# signal that is bi-directional. The internal BREQ# signals are mapped onto BR# pins based on a
processor’s agent ID. See Chapter 10 for more information.
2. For information on these signals, see Chapter 10.
3. These signals are specified for 2.5V operation.
4. V
TT
is used for the AGTL+ termination.
V
SS
is system ground.
Vcc_
TAP
is the TAP supply.
Vcc_
SMB
is the SM bus supply.
Reserved pins must be left unconnected. Do not connect to each other.
3.7.2 ASYNCHRONOUS VS. SYNCHRONOUS FOR SYSTEM BUS SIGNALS
All AGTL+ signals are synchronous to BCLK. All of the CMOS, Clock, APIC, and TAP signals can be applied
asynchronously to BCLK.
All APIC signals are synchronous to PICCLK. All TAP signals are synchronous to TCK. All SMBus signals are
synchronous to SMBCLK. TCK and SMBCLK can be asynchronous to all other clocks.
3.8 Access Port (TAP) Connection
Depending on the voltage levels supported by other components in the Test Access Port (TAP) logic, it is recommended
that the processor be first in the TAP chain and followed by any other components within the system. A voltage translation
buffer should be used to drive the next device in the chain unless a component is used that is capable of accepting a 2.5V
input. Similar considerations must be made for TCK, TMS, and TRST#. Multiple copies of each TAP signal may be
required if multiple voltage levels are needed within a system.
NOTE
TDI is pulled up to V
cc
TAP
with ~150Ω
ΩΩ
Ω on the processor cartridge. An open drain signal driving this pin
must be able to deliver sufficient current to drive the signal low. Also, no resistor should exist in the
system design on this pin, as it would be in parallel with this resistor.