Datasheet

ELECTRICAL SPECIFICATIONS
15
Table 2. FMB Core and L2 Voltage Identification Definition
1, 2
Processor pins
VID4 VID3 VID2 VID1 VID0 Vcc Core
3
L2
3,5
00110b – 01111b Reserved
2
0 0 1 0 1 1.80 X X
0 0 1 0 0 1.85 X X
0 0 0 1 1 1.90 X X
0 0 0 1 0 1.95 X X
0 0 0 0 1 2.00 X X
0 0 0 0 0 2.05 X X
1 1 1 1 0 2.1 X X
1 1 1 0 1 2.2 X
1 1 1 0 0 2.3 X
1 1 0 1 1 2.4 X
1 1 0 1 0 2.5 X
1 1 0 0 1 2.6 X
1 1 0 0 0 2.7 X
1 0 1 1 1 2.8
6
X X
1 0 1 1 0 2.9
1 0 1 0 1 3.0
1 0 1 0 0 3.1
1 0 0 1 1 3.2
1 0 0 1 0 3.3
1 0 0 0 1 3.4
1 0 0 0 0 3.5
1 1 1 1 1 No core
7
Core
4
NOTES:
1. 0 = processor pin connected to VSS, 1 = Open on processor; may be pulled up to TTL V
IH
on baseboard. See the VRM 8.3 DC–DC
Converter Design Guidelines and/or the VRM 8.3 DC–DC Converter Design Guidelines.
2. VRM output should be disabled for VCC_
CORE
values less than 1.80V.
3. X = Required.
4. The Pentium® III Xeon™ processor at 700 MHz and 900 MHz does not require an L2 voltage supply. The VCC_L2 and L2 VID lines
are ”open” on the processor cartridge.
5. Required for FMB compatibility, not necessary for the Pentium® III Xeon™ processor at 700 MHz and 900 MHz.
6. This VID setting can be used in combination with HV_EN# pin (A3) for differentiating 2.8V version from 5V/12V version cartridges.
7. The Pentium® III Xeon™ processor at 700 MHz and 900 MHz incorporates an integrated L2 cache, which eliminates the requirement
of a VRM to power the L2 cache. Legacy systems provide L2 VRMs for Pentium® II Xeon™ processor or Pentium® III Xeon™
processor at 500 MHz and 550 MHz support. In these legacy systems, the Pentium® III Xeon™ processor at 700 MHz and 900 MHz
will pass VID[4:0] = 11111 to the L2 VRM, instructing it to disable its output voltage. Certain VRM designs will also de-assert their
VRM_PWRGD output. VRM_PWRGD signals are generally used to derive a SYS_PWRGD signal. With VRM_PWRGD de-asserted,
the SYS_PWRGD is likely to be de-asserted, and the system will not boot. OEMs should examine legacy system and VRM designs
intended to support the Pentium® III Xeon™ processor at 700 MHz and 900 MHz to ensure that there is no adverse impact to
SYS_PWRGD derivation. See Figures 41 and 42.
The VID pins should be pulled up to a TTL-compatible level with external resistors to the power source of the regulator
only if required by the regulator or external logic monitoring the VID[4:0] signals. The power source chosen to drive/pull up
VIDs must be guaranteed to be stable whenever the supply to the voltage regulator is non-zero and the OCVR is enabled.
An invalid VID while the output is coming up could lead to and incorrect voltage above VCC_
CORE
max. This will prevent
the possibility of the processor supply going above VCC_
CORE
in the event of a failure in the supply for the VID lines. In
the case of a DC-to-DC converter, this can be accomplished by using the input voltage to the converter for the VID line