Datasheet

APPENDIX
103
Table 61. Input Signals
Name Active Level Clock Signal Group Qualified
A20M# Low Asynch CMOS Input Always
BPRI# Low BCLK AGTL+ Input Always
BR[3:1]# Low BCLK AGTL+ Input Always
BCLK High — System Bus Clock Always
DEFER# Low BCLK AGTL+ Input Always
FLUSH# Low Asynch CMOS Input Always
2
IGNNE# Low Asynch CMOS Input Always
2
INIT# Low Asynch CMOS Input Always
2
INTR High Asynch CMOS Input APIC disabled mode
LINT[1:0] High Asynch CMOS Input APIC enabled mode
NMI High Asynch CMOS Input APIC disabled mode
PICCLK High — APIC Clock Always
PREQ# Low Asynch CMOS Input Always
PWRGD High Asynch CMOS Input Always
RESET# Low BCLK AGTL+ Input Always
RS[2:0]# Low BCLK AGTL+ Input Always
RSP# Low BCLK AGTL+ Input Always
SA[2:0] High SMBCLK Power/Other
SMBCLK# High — SMBus Clock Always
SLP# Low Asynch CMOS Input During Stop Grant state
SMI# Low Asynch CMOS Input
STPCLK# Low Asynch CMOS Input
TCK High — TAP Clock
TDI High TCK TAP Input
TMS High TCK TAP Input
TRST# Low Asynch TAP Input
TRDY# Low BCLK AGTL+ Input
WP High Asynch SMBus Input
OCVR_EN High Asynch Power/Other
Table 62. I/O Signals (Single Driver)
Name Active Level Clock Signal Group Qualified
A[35:03]# Low BCLK AGTL+ I/O ADS#, ADS#+1
ADS# Low BCLK AGTL+ I/O Always
AP[1:0]# Low BCLK AGTL+ I/O ADS#, ADS#+1
SELFSB0 High — Power/Other