Datasheet

Datasheet 5
Figures
1 Second Level (L2) Cache Implementation ...........................................................9
2 AGTL+ Bus Topology..........................................................................................14
3 Stop Clock State Machine...................................................................................14
4 BSEL[1:0] Example for a 100 MHz System Design (100 MHz Processor
Installed)..............................................................................................................22
5 BSEL[1:0] Example for a 100/133 MHz Capable System
(100 MHz Processor Installed)............................................................................23
6 BSEL[1:0] Example for a 100/133 MHz Capable System
(133 MHz Processor Installed)............................................................................23
7 BCLK, PICCLK, and TCK Generic Clock Waveform...........................................37
8 System Bus Valid Delay Timings ........................................................................38
9 System Bus Setup and Hold Timings..................................................................38
10 System Bus Reset and Configuration Timings....................................................38
11 Power-On Reset and Configuration Timings.......................................................39
12 Test Timings (TAP Connection) ..........................................................................39
13 Test Reset Timings .............................................................................................39
14 BCLK and PICCLK Generic Clock Waveform.....................................................40
15 Maximum Acceptable AGTL+ and Non-AGTL+ Overshoot/Undershoot
Waveform ............................................................................................................46
16 Low to High AGTL+ and Non-AGTL+ Receiver Ringback Tolerance .................48
17 Signal Overshoot/Undershoot, Settling Limit, and Ringback...............................48
18 S.E.C.Cartridge — 3-Dimensional View..............................................................49
19 S.E.C.Cartridge 2 — Substrate View ..................................................................50
20 Processor Functional Die Layout (CPUID=0686h)..............................................52
21 Processor Functional Die Layout (up to CPUID=0683h).....................................52
22 S.E.C.C. Packaged Processor — Multiple Views................................................54
23 S.E.C.C. Packaged Processor — Extended Thermal Plate Side
Dimensions..........................................................................................................55
24 S.E.C.C. Packaged Processor — Bottom View Dimensions...............................55
25 S.E.C.C. Packaged Processor — Latch Arm, Extended Thermal Plate Lug,
and Cover Lug Dimensions.................................................................................56
26 S.E.C.C. Packaged Processor — Latch Arm, Extended Thermal Plate,
and Cover Detail Dimensions (Reference Dimensions Only)..............................57
27 S.E.C.C. Packaged Processor — Extended Thermal Plate Attachment
Detail Dimensions ...............................................................................................58
29 S.E.C.C. Packaged Processor Substrate — Edge Finger Contact
Dimensions..........................................................................................................59
28 S.E.C.C. Packaged Processor — Extended Thermal Plate Attachment
Detail Dimensions, Continued.............................................................................59
30 S.E.C.C. Packaged Processor Substrate — Edge Finger Contact
Dimensions, Detail A...........................................................................................60
31 Intel
®
Pentium® III Processor Markings (S.E.C.C. Packaged Processor)...........60
32 S.E.C.C.2 Packaged Processor — Multiple Views..............................................61
33 S.E.C.C.2 Packaged Processor Assembly — Primary View...............................62
34 S.E.C.C.2 Packaged Processor Assembly — Cover View with Dimensions ......62
35 S.E.C.C.2 Packaged Processor Assembly — Heatsink Attach Boss Section.....63
36 S.E.C.C.2 Packaged Processor Assembly — Side View....................................63
37 Detail View of Cover in the Vicinity of the Substrate Attach Features.................63
38 S.E.C.C.2 Packaged Processor Substrate — Edge Finger Contact
Dimensions..........................................................................................................64