Datasheet

Datasheet 37
Electrical Specifications
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processor frequencies.
2. All AC timings for the TAP signals are referenced to the TCK rising edge at 1.25 V (CPUID=067xh) or 0.75 V
(CPUID=068xh) at the processor core pins. All TAP signal timings (TMS, TDI, etc.) are referenced at 1.25 V
(CPUID=067xh) or 0.75 V (CPUID=068xh) at the processor core pins.
3. These specifications are tested during manufacturing, unless otherwise noted.
4. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16.667 MHz.
5. Referenced to TCK rising edge.
6. Referenced to TCK falling edge.
7. Valid delay timing for this signal is specified to 2.5 V +5%.
8. Non-Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and
TMS). These timings correspond to the response of these signals due to TAP operations.
9. During Debug Port operation, use the normal specified timings rather than the TAP signal timings.
10.Not 100% tested. Specified by design characterization.
11.This specification applies to the Pentium III processor with CPUID=067xh.
12.This specification applies to the Pentium III processor with CPUID=068xh.
Note: For Figure 7 through Figure 13, the following apply:
1. Figure 7 through Figure 13 are to be used in conjunction with Table 12 through Table 18.
2. All AC timings for the AGTL+ signals at the processor core pins are referenced to the BCLK
rising edge at 1.25 V. All AGTL+ signal timings (address bus, data bus, etc.) are referenced at
1.00 V at the processor core pins.
T43: All Non-Test Inputs Setup Time 5.0 ns 12 5, 8, 9
T44: All Non-Test Inputs Hold Time 13.0 ns 12 5, 8, 9
Table 18. System Bus AC Specifications (TAP Connection) at the Processor Core Pins
T# Parameter Min Max Unit Figure Notes
1, 2, 3
Figure 7. BCLK, PICCLK, and TCK Generic Clock Waveform
T
r
= T5, T25, T34, (Rise Time)
T
f
= T6, T26, T35, (Fall Time)
T
h
= T3, T23, T32, (High Time)
T
l
= T4, T24, T33, (Low Time)
T
p
= T1, T22, T31 (BCLK, TCK, PICCLK Period)
V1 = BCLK = 0.5V, PICCLK = 0.7V, and TCK = 0.7V (CPUID 067xh) or V
REF
- 0.20V (CPUID 068xh)
V2 = BCLK = 1.25V, PICCLK = 1.25V and TCK = 1.25V (CPUID 067xh) or 0.75V (CPUID 068xh)
V3 = BCLK = 2.0V, PICCLK = 1.7V (CPUID 067xh) or 2.0V (CPUID 068xh),
TCK = 1.7V (CPUID 067xh) or V
REF
- 0.20V (CPUID 068xh)
V3
V2
V1
t
r
t
p
t
f
t
h
t
l
CLK