Datasheet

36 Datasheet
Electrical Specifications
.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processor frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the APIC I/O signals are referenced to the PICCLK rising edge at 1.25 V at the processor
core pins. All APIC I/O signal timings are referenced at 1.25 V (CPUID=067xh) or 0.75 V (CPUID=068xh) at
the processor core pins.
4. Referenced to PICCLK rising edge.
5. For open drain signals, valid delay is synonymous with float delay.
6. Valid delay timings for these signals are specified into a 150 Ω load pulled up to 2.5 V +5%.
7. This specification applies to the Pentium III processor with CPUID=067xh.
8. This specification applies to the Pentium III processor with CPUID=068xh.
Table 17. System Bus AC Specifications (APIC Clock and APIC I/O) at the
Processor Core Pins
T# Parameter Min Max Unit Figure Notes
1, 2, 3
T21: PICCLK Frequency 2.0 33.3 MHz
T22: PICCLK Period 30.0 500.0 ns 7
T23: PICCLK High Time 12.0 ns 7
T24: PICCLK Low Time 12.0 ns 7
T25: PICCLK Rise Time 0.25 3.0 ns 7
T26: PICCLK Fall Time 0.25 3.0 ns 7
T27: PICD[1:0] Setup Time
8.0
5.0
ns
ns
9
9
4, 7
4, 8
T28: PICD[1:0] Hold Time 2.5 ns 9 4
T29: PICD[1:0] Valid Delay 1.5 10 ns 8 4, 5, 6, 7
T29a: PICD[1:0] Valid Delay (Rising Edge) 1.5 8.7 ns 8 4, 5, 6, 8
T29b: PICD[1:0] Valid Delay (Falling Edge) 1.5 12.0 ns 8 4, 5, 6, 8
Table 18. System Bus AC Specifications (TAP Connection) at the Processor Core Pins
T# Parameter Min Max Unit Figure Notes
1, 2, 3
T30: TCK Frequency 16.667 MHz
T31: TCK Period 60.0 ns 7
T32: TCK High Time
25.0
25.0
ns
ns
7
7
@1.7 V
10, 11
@V
REF
+ 0.20 V
10, 12
T33: TCK Low Time
25.0
25.0
ns
ns
7
7
@0.7 V
10, 11
@V
REF
– 0.20 V
10, 12
T34: TCK Rise Time
5.0
5.0
ns
ns
7
7
(0.7 V–1.7 V)
4, 10, 11
(V
REF
– 0.20 V) –
(V
REF
+ 0.20 V)
10, 12
T35: TCK Fall Time
5.0
5.0
ns
ns
7
7
(1.7 V–0.7 V)
4, 10
(V
REF
+ 0.20 V) –
(V
REF
– 0.20 V)
10, 12
T36: TRST# Pulse Width 40.0 ns 13 Asynchronous
10
T37: TDI, TMS Setup Time 5.0 ns 12 5
T38: TDI, TMS Hold Time 14.0 ns 12 5
T39: TDO Valid Delay 1.0 10.0 ns 12 6, 7
T40: TDO Float Delay 25.0 ns 12 6, 7, 10
T41: All Non-Test Outputs Valid Delay 2.0 25.0 ns 12 6, 8, 9
T42: All Non-Test Inputs Setup Time 25.0 ns 12 6, 8, 9, 10