Datasheet

Datasheet 35
Electrical Specifications
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processor frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25 V at the processor core
pin. All AGTL+ signal timings (compatibility signals, etc.) are referenced at 1.00 V at the processor core pins.
4. Valid delay timings for these signals are specified into 25 Ω to 1.5 V and with V
REF
at 1.0 V.
5. Valid delay timings for these signals are specified into 50 Ω to 1.5 V and with V
REF
at 1.0 V.
6. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
7. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously. For 2-way MP
systems, RESET# should be synchronous.
8. Specification is for a minimum 0.40 V swing.
9. Specification is for a maximum 1.0 V swing.
10.This should be measured after V
CC
CORE
, VCC
L2
/VCC
3.3
, and BCLK become stable.
11.This specification applies to the Pentium III processor with a system bus frequency of 100 MHz.
12.This specification applies to the Pentium III processor with a system bus frequency of 133 MHz.
13.This specification applies to the Pentium III processor with CPUID=067xh.
14.This specification applies to the Pentium III processor with CPUID=068xh.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processor frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the CMOS signals are referenced to the BCLK rising edge at 0.7 V at the processor core
pins. All CMOS signal timings (compatibility signals, etc.) are referenced at 1.25 V.
4. These signals may be driven asynchronously.
5. When driven inactive or after V
CC
CORE
, VCC
L2
/VCC
3.3
, and BCLK become stable.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processor frequencies.
Table 14. System Bus AC Specifications (AGTL+ Signal Group) at the
Processor Core Pins
T# Parameter Min Max Unit Figure Notes
1, 2, 3
T7: AGTL+ Output Valid Delay
-0.20
-0.14
-0.10
3.15
2.20
2.70
ns
ns
ns
8
8
8
4, 10, 13
5, 11, 13
5, 11, 12, 14
T8: AGTL+ Input Setup Time
1.90
1.20
1.20
ns
ns
ns
9
9
9
6, 7, 8, 11, 13
6, 7, 8, 12, 13
6, 7, 8, 11, 12, 14
T9: AGTL+ Input Hold Time
0.85
0.58
0.80
ns
ns
ns
9
9
9
9, 11, 13
9, 12, 13
9, 11, 12, 14
T10: RESET# Pulse Width 1.00 ms 11 7, 10
Table 15. System Bus AC Specifications (CMOS Signal Group) at the Processor Core Pins
T# Parameter Min Max Unit Figure Notes
1, 2, 3, 4
T14: CMOS Input Pulse Width, except
PWRGOOD
2BCLKs8
Active and Inactive
states
T15: PWRGOOD Inactive Pulse Width 10 BCLKs 8, 11 5
Table 16. System Bus AC Specifications (Reset Conditions)
T# Parameter Min Max Unit Figure Notes
1
T16: Reset Configuration Signals
(A[14:5]#, BR0#, FLUSH#,
INIT#) Setup Time
4BCLKs10
Before deassertion
of RESET#
T17: Reset Configuration Signals (A[14:5]#,
BR0#, FLUSH#, INIT#) Hold Time
220BCLKs10
After clock that
deasserts RESET#