Datasheet

Datasheet 3
Contents
1.0 Introduction.........................................................................................................................9
1.1 Terminology.........................................................................................................10
1.1.1 S.E.C.C.2 and S.E.C.C. Packaged Processor Terminology ..................10
1.1.2 Processor Naming Convention...............................................................11
1.2 Related Documents.............................................................................................12
2.0 Electrical Specifications....................................................................................................13
2.1 Processor System Bus and V
REF
........................................................................13
2.2 Clock Control and Low Power States..................................................................14
2.2.1 Normal State—State 1 ...........................................................................15
2.2.2 AutoHALT Powerdown State—State 2...................................................15
2.2.3 Stop-Grant State—State 3 .....................................................................15
2.2.4 HALT/Grant Snoop State—State 4 ........................................................16
2.2.5 Sleep State—State 5..............................................................................16
2.2.6 Deep Sleep State—State 6 ....................................................................16
2.2.7 Clock Control..........................................................................................17
2.3 Power and Ground Pins ......................................................................................17
2.4 Decoupling Guidelines ........................................................................................17
2.4.1 Processor VCC
CORE
Decoupling............................................................18
2.4.2 Processor System Bus AGTL+ Decoupling............................................18
2.5 Processor System Bus Clock and Processor Clocking.......................................18
2.6 Voltage Identification...........................................................................................18
2.7 Processor System Bus Unused Pins...................................................................20
2.8 Processor System Bus Signal Groups ................................................................20
2.8.1 Asynchronous vs. Synchronous for System Bus Signals.......................21
2.8.2 System Bus Frequency Select Signal (BSEL0)......................................22
2.9 Test Access Port (TAP) Connection....................................................................23
2.10 Maximum Ratings................................................................................................24
2.11 Processor DC Specifications...............................................................................25
2.12 AGTL+ System Bus Specifications .....................................................................32
2.13 System Bus AC Specifications ............................................................................32
3.0 Signal Quality Specifications............................................................................................40
3.1 BCLK, PICCLK, and PWRGOOD Signal Quality Specifications and
Measurement Guidelines ....................................................................................40
3.2 AGTL+ and Non-AGTL+ Overshoot/Undershoot Specifications and
Measurement Guidelines ....................................................................................41
3.2.1 Overshoot/Undershoot Magnitude .........................................................41
3.2.2 Overshoot/Undershoot Pulse Duration...................................................42
3.2.3 Overshoot/Undershoot Activity Factor....................................................42
3.2.4 Reading Overshoot/Undershoot Specification Tables............................43
3.2.5 Determining If a System Meets the Overshoot/Undershoot
Specifications .........................................................................................44
3.3 AGTL+ and Non-AGTL+ Ringback Specifications and Measurement
Guidelines ...........................................................................................................46
3.3.1 Settling Limit Guideline...........................................................................48