Datasheet
Datasheet 29
Electrical Specifications
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. This specification applies to Pentium III processors. For baseboard compatibility information on Pentium II
processors, refer to the Intel
®
Pentium
®
II Processor at 350, 400 and 450 MHz datasheet (Document Number
243657).
3. V
CC
CORE
and Icc
CORE
supply the processor core.
4. A variable voltage source should exist on all systems in the event that a different voltage is required. See
Table 3 for more information.
5. Use the Typical Voltage specification with the Tolerance specifications to provide correct voltage regulation to
the processor.
6. V
TT must be held to 1.5 V ±9%. It is recommended that VTT be held to 1.5 V ±3% while the Pentium III
processor system bus is idle. This is measured at the processor edge fingers across a 20 MHz bandwidth.
7. These are the tolerance requirements, across a 20 MHz bandwidth, at the SC242 connector pin on the
bottom side of the baseboard. The requirements at the SC242 connector pins account for voltage drops (and
impedance discontinuities) across the connector, processor edge fingers, and to the processor core.
V
CC
CORE
must return to within the static voltage specification within 100 µs after a transient event; see the
VRM 8.4 DC-DC Converter Design Guidelines (Document Number 245335) for further details.
8. These are the tolerance requirements, across a 20 MHz bandwidth, at the processor edge fingers. The
requirements at the processor edge fingers account for voltage drops (and impedance discontinuities) at the
processor edge fingers and to the processor core. V
CC
CORE
must return to within the static voltage
specification within 100 µs after a transient event.
I
SLP
ICC Sleep for processor
core
450 MHz
500 MHz
533B MHz
533EB MHz
550 MHz
550E MHz
600 MHz
600B MHz
600E MHz
600EB MHz
650 MHz
667 MHz
700 MHz
733 MHz
750 MHz
800 MHz
800EB MHz
850 MHz
866 MHz
933 MHz
1.0 GHz
1.0B GHz
ALL
0.80
0.90
1.00
2.50
1.00
2.50
1.00
1.00
2.50
2.50
2.50
2.50
2.50
2.50
2.50
2.50
2.50
2.50
2.50
2.50
2.50
2.50
A
2, 10
2, 10
2, 10
2, 10
2, 10
2, 10
2, 10
2, 10
2, 10
2, 10
2, 10
2, 10
2, 10
2, 10
2, 10
2, 10
2, 10
2, 10
2, 10
2, 10
2, 10
2, 10
I
SL
PL2
ICC Sleep for second level
cache
0.1 A 2, 9, 10, 18
I
DSLP
ICC Deep Sleep for
processor core
0.50
2.20
3.00
A
2, 10, 18
2, 10, 19
2, 10
I
DSL
PL2
ICC Deep Sleep for
second level cache
0.1 A 2, 9, 10, 18
dI
CC
CORE
/dt
Power supply current slew
rate
20 A/µs 2, 14, 15, 16
dI
CC
L2
/dt
L2 cache power supply
current slew rate
1A/µs 14, 15, 16, 18
dI
CC
V
TT
/dt
Termination current slew
rate
8A/µs
14, 15, See
Table 11
V
CC
5
5 V supply voltage 4.75 5.00 5.25 V 5 V ±5%
16, 17
ICC
5
ICC for 5 V supply voltage 1.0 A 17
Table 8. Voltage and Current Specifications (Sheet 4 of 4)
Symbol Parameter
Processor
Min Typ Max Unit Notes
1
Core Freq CPUID