Datasheet

Datasheet 21
Electrical Specifications
NOTES:
1. The BR0# pin is the only BREQ# signal that is bidirectional. The internal BREQ# signals are mapped onto
BR# pins after the agent ID is determined. See Section 7.0 for more information.
2. See Section 7.0 for information on the PWRGOOD signal.
3. See Section 7.0 for information on the SLP# signal.
4. See Section 7.0 for information on the THERMTRIP# signal.
5. These signals are specified for 2.5 V operation.
6. V
CC
CORE
is the power supply for the processor core.
V
CC
L2
/VCC
3.3
is described in Section 2.3.
VID[4:0] is described in Section 2.6.
V
TT is used to terminate the system bus and generate V
REF
on the processor substrate.
V
SS is system ground.
TESTHI should be connected to 2.5 V with a 1 kΩ –10 kΩ resistor.
V
CC
5
is not connected to the Pentium III processor core. This supply is used for the test equipment and tools.
SLOTOCC# is described in Section 7.0.
BSEL[1:0] is described in Section 2.8.2 and Section 7.0.
EMI pins are described in Section 7.0.
THERMDP, THERMDN are described in Section 7.0.
2.8.1 Asynchronous vs. Synchronous for System Bus Signals
All AGTL+ signals are synchronous to BCLK. All of the CMOS, Clock, APIC, and TAP signals
can be applied asynchronously to BCLK.
All APIC signals are synchronous to PICCLK. All TAP signals are synchronous to TCK.
Table 4. System Bus Signal Groups
Group Name Signals
AGTL+ Input BPRI#, BR1#, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY#
AGTL+ Output PRDY#
AGTL+ I/O
A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#,
BR0#
1
, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#, LOCK#, REQ[4:0]#, RP#
CMOS Input
5
A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, PWRGOOD
2
,
SMI#, SLP#
3
, STPCLK#
CMOS Output
5
FERR#, IERR#, THERMTRIP#
4
System Bus Clock BCLK
APIC Clock PICCLK
APIC I/O
5
PICD[1:0]
TAP Input
5
TCK, TDI, TMS, TRST#
TAP Output
5
TDO
Power/Other
6
VCC
CORE
, VCC
L2
/VCC
3.3
, VCC
5
, VID[4:0], VTT, VSS, SLOTOCC#, THERMDP, THERMDN,
BSEL[1:0], EMI, TESTHI, Reserved