Datasheet

Pentium
®
III Xeon™ Processor at 500 and 550 MHz
Datasheet
41
4.3.1 Processor Information ROM
An electrically programmed read-only memory with information about the Pentium
III
Xeon
processor is provided on the processor substrate. This information is permanently write-protected.
Table 23 shows the data fields and formats provided in the memory.
Table 23. Processor Information ROM Format (Sheet 1 of 2)
Offset/Section # of Bits Function Notes
HEADER: 00h 8 Data Format Revision Two 4-bit hex digits
01h 16 EEPROM Size Size in bytes (MSB first)
03h 8 Processor Data Address Byte pointer, 00h if not present
04h 8 Processor Core Data Address Byte pointer, 00h if not present
05h 8 L2 Cache Data Address Byte pointer, 00h if not present
06h 8 SEC Cartridge Data Address Byte pointer, 00h if not present
07h 8 Part Number Data Address Byte pointer, 00h if not present
08h 8
Thermal Reference Data
Addres
Byte pointer, 00h if not present
09h 8 Feature Data Address Byte pointer, 00h if not present
0Ah 8 Other Data Address Byte pointer, 00h if not present
0Bh 16 Reserved Reserved for future use
0Dh 8 Checksum 1 byte checksum
PROCESSOR: 0Eh 48 S-spec/QDF Number Six 8-bit ASCII characters
2 Sample/Production 00b = Sample only
6 Reserved Reserved for future use
8 Checksum 1 byte checksum
CORE: 16h 2 Processor Core Type From CPUID
4 Processor Core Family From CPUID
4 Processor Core Model From CPUID
4 Processor Core Steppin From CPUID
42 Reserved Reserved for future use
16 Maximum Core Frequency 16-bit binary number (in MHz)
16 Core Voltage ID Voltage in mV
8 Core Voltage Tolerance, Hig Edge finger tolerance in mV, +
8 Core Voltage Tolerance, Low Edge finger tolerance in mV,
8 Reserved Reserved for future use
8 Checksum 1 byte checksum
L2 CACHE: 25h 32 Reserved Reserved for future use
16 L2 Cache Size 16-bit binary number (in Kbytes
4 Number of SRAM Components One 4-bit hex digit
4 Reserved Reserved for future use
16 L2 Cache Voltage ID Voltage in mV