Datasheet

Pentium
®
III Xeon™ Processor at 500 and 550 MHz
Datasheet
29
Figure 4 through Figure 12 are to be used in conjunction with the DC specification and AC timings
tables.
Figure 4. BCLK, PICCLK, TCK Generic Clock Waveform
Figure 5. SMBCLK Clock Waveform
Figure 6. Valid Delay Timings
1.25 V
0.5 V
2.0 V
T
p
T
f
T
r
Clock
T
h
T
l
T5, T25, T34 (Rise Time)
T6, T26, T36 (Fall Time)
T3, T23, T32 (High Time)
T4, T24, T33 (Low Time)
T1, T22, T31 (BCLK, PICCLK, TCK, Period)
T
r
=
T
f
=
T
h
=
T
l
=
T
p
=
SCLK
2.46V
0.84V
T
h
T
l
T
r
T
f
T
r
T54
T
f
T55
T52
T
h
T53
T
l
=
=
=
=
2.97V
0.84V
Clock
Signal
T
x
T
x
T
pw
V Valid Valid
T
x
T7, T11, T29 (Valid Delay)
=
T
pw
T14, T15 (Pulse Wdith)
=
V
2/3 V
TT
for GTL+ signal group; 1.25V for CMOS, and APIC signal groups=