Datasheet

Pentium
®
III Xeon™ Processor at 500 and 550 MHz
24
Datasheet
NOTES:
1. (0
≤
V
IN
≤
2.62 5V).
2. (0
≤
V
OUT
≤
2.62 5V).
† SMBALERT# is an open drain signal.
2.11 AGTL+ System Bus Specifications
Table 10 below lists parameters controlled within the Pentium
III
Xeon processor to be taken into
consideration during simulation. The valid high and low levels are determined by the input buffers
using a reference voltage (V
REF
) which is generated internally in the processor cartridge from V
TT
.
V
REF
should be set to the same level for other AGTL+ logic using a voltage divider on the
baseboard. It is important that the baseboard impedance be specified and held to a ±10% tolerance,
and that the intrinsic trace capacitance for the AGTL+ signal group traces is known and well-
controlled. For more details on AGTL+, see the
100 MHz 2-Way SMP Pentium
®
III
Xeon™
Processor/Intel
®
440GX AGPset AGTL+ Layout Guidelines
and
Pentium
®
III
Xeon™ Processor/
Intel
®
450NX PCIset AGTL+ Layout Guidelines
. Also refer to the
Pentium
®
II Processor
Developer’s Manual
for the GTL+ buffer specification.
Table 8. CMOS, TAP, Clock and APIC Signal Groups, DC Specifications at the Processor
Core
Symbol Parameter Min Max Unit Notes
V
IL
Input Low Voltage -0.3 0.7 V
V
IH
Input High Voltage 1.7 2.625 V 2.5 V + 5% maximum
V
OL
Output Low Voltag 0.5 V Measured at 24mA
V
OH
Output High Voltage 2.625 V All outputs are open-drai n to 2.5V + 5%
I
OL
Output Low Current 24 mA
I
LI
Input Leakage Current ±100 µA 1
I
LO
Output Leakage
Current
±30 µA 2
Table 9. SMBus Signal Group, DC Specifications at the Processor Core
Symbol Parameter Min Max Unit Notes
V
IL
Input Low Voltage -0.3
0.3 x
V
CC
SMB
US
V
V
IH
Input High Voltage 0.7 x V
CC
SMB
US
3.465 V 3.3 V + 5% maximum
V
OL
Output Low Voltage 0.4 V
I
OL
Output Low Current 3 mA Except SMBALERT#
I
OL2
Output Low Current 6 mA SMBALERT#
†
I
LI
Input Leakage Current 10 µA
I
LO
Output Leakage
Current
10 µA