Datasheet

Pentium
®
III Xeon™ Processor at 500 and 550 MHz
20
Datasheet
2.9 Maximum Rating
Table 4 contains Pentium
III
Xeon processor stress ratings. Functional operation at the absolute
maximum and minimum is not implied nor guaranteed. The processor should not receive a clock
while subjected to these conditions. Functional operating conditions are given in the AC and DC
tables. Extended exposure to the maximum ratings may affect device reliability. Furthermore,
although the processor contains protective circuitry to resist damage from static electric discharge,
one should always take precautions to avoid high static voltages or electric fields.
NOTES:
1. Operating voltage is the voltage to which the component is designed to operate. See Table 5.
2. This parameter specifies that the processor will not be immediately damaged by either supply being disabled.
2.10 Processor DC Specifications
The voltage and current specifications provided in Table 5 and Table 6 are defined at the processor
edge fingers. The processor signal DC specifications in Table 7, Table 8, and Table 9 are defined at
the Pentium
III
Xeon processor core. Each signal trace between the processor edge finger and the
processor core carries a small amount of current and has a finite resistance. The current produces a
voltage drop between the processor edge finger and the core. Simulations should therefore be run
versus these specifications to the processor core.
See Section 9.0 for the processor edge finger signal definitions and Table 3 for the signal grouping.
Table 4. Pentium
®
III Xeon™ Processor Absolute Maximum Ratings
Symbol Parameter Min Max Unit Notes
T
STORAGE
Processor storage temperature –40 85 °C
V
CC
CORE
Processor core supply voltage with
respect to V
SS
–0.5
Operating
voltage + 1.0
V1
V
CC
L2
Any processor L2 supply voltage with
respect to V
SS
–0.5
Operating
voltage + 1.0
V1
V
SMB
US
Any processor SM supply voltage with
respect to V
SS
-0.3
Operating
voltage + 1.0
V
V
CC
TA P
Any processor TAP supply voltage with
respect to V
SS
-0.3 3.3 V 1
V
CC
L2
–
V
CC
CORE
L2 supply voltage with respect to core
voltage.
-(Core
Operating
Voltage
L2 Operating
Voltage
V1, 2
V
in
GTL
AGTL+ buffer DC input voltage with
respect to V
SS
–0.3
V
CC
CORE
+
0.7
V
V
in
CMOS
CMOS & APIC buffer DC input voltage
with respect to V
SS
–0.3 3.3 V
V
in
SMBus
SMBus buffer DC input voltage with
respect to V
SS
-0.1 6.0 V
I
PWR_EN
Max PWR_EN[1:0] pin current 100 mA
I
VID
Max VID pin current 5 mA