Datasheet

Datasheet
107
Pentium
®
III Xeon™ Processor at 500 and 550 MHz
1 Core Frequency to System Bus Multiplier Configuration.................................... 14
2 Core and L2 Voltage Identification Definition
1, 2...................................................................16
3Pentium
®
III Xeon™ Processor System Bus Pin Groups ................................... 18
4Pentium
®
III Xeon™ Processor Absolute Maximum Ratings.............................. 20
5 Voltage Specifications
1 .....................................................................................................................21
6 Current Specifications
1......................................................................................................................22
7 AGTL+ Signal Groups, DC Specifications at the Processor Core...................... 23
8 CMOS, TAP, Clock and APIC Signal Groups, DC Specifications at the Processor Core24
9 SMBus Signal Group, DC Specifications at the Processor Core........................ 24
10 Pentium
®
III Xeon™ Processor Internal Parameters for the AGTL+ Bus........... 25
11 System Bus AC Specifications (Clock) at the Processor Core........................... 25
12 AGTL+ Signal Groups, System Bus AC Specifications at the Processor Core
1..26
13 CMOS, TAP, Clock and APIC Signal Groups, AC Specifications at the Processor Core
1, 226
14 System Bus AC Specifications (Reset Conditions)............................................. 27
15 System Bus AC Specifications (APIC Clock and APIC I/O) at the Processor Core
127
16 System Bus AC Specifications (TAP Connection) at the Processor Core
1 ............28
17 SMBus Signal Group, AC Specifications at the Edge Fingers............................ 28
18 BCLK Signal Quality Specifications for Simulation at the Processor Core
1 ...........33
19 AGTL+ Signal Groups Ringback Tolerance Specifications at the Processor Core
1, 2, 334
20 AGTL+ Overshoot/Undershoot Guidelines at the Processor Core..................... 35
21 2.5 V Tolerant Signal Overshoot/Undershoot Guidelines at the Processor Core35
22 Signal Ringback Specifications for 2 .5V Tolerant Signal Simulation at the Processor Core36
23 Processor Information ROM Format................................................................... 41
24 Current Address Read SMBus Packet ............................................................... 43
25 Random Address Read SMBus Packet.............................................................. 43
26 Byte Write SMBus Packet................................................................................... 43
27 Write Byte SMBus Packet................................................................................... 45
28 Read Byte SMBus Packet .................................................................................. 45
29 Send Byte SMBus Packet................................................................................... 45
30 Receive Byte SMBus Packet.............................................................................. 45
31 ARA SMBus Packet............................................................................................ 45
32 Command Byte Bit Assignments ........................................................................ 45
33 Thermal Sensor Status Register......................................................................... 47
34 Thermal Sensor Configuration Register ............................................................. 47
35 Thermal Sensor Conversion Rate Register........................................................ 48
36 Thermal Sensor SMBus Addressing on the Pentium
®
III Xeon™ Processor ..... 49
37 Memory Device SMBus Addressing on the Pentium
®
III Xeon™ Processor...... 49
38 Thermal Design Power
1....................................................................................................................51
39 Example Thermal Solution Performance at Thermal Plate Power of 50 Watts .. 52
40 Signal Listing in Order by Pin Number................................................................ 62
41 Signal Listing in Order by Pin Name................................................................... 66
42 Boxed Processor Heatsink Dimensions.............................................................. 73
43 Fan/Heatsink Power and Signal Specifications .................................................. 78
44 Debug Port Pinout Description and Requirements
1 ...........................................................80
45 BR[3:0]# Signals Rotating Interconnect, 4-Way System .................................... 89
46 BR[3:0]# Signals Rotating Interconnect, 2-Way System .................................... 89
47 Agent ID Configuration ....................................................................................... 89
48 Output Signals
†.....................................................................................................................................98
49 Input Signals
1.........................................................................................................................................99
50 I/O Signals (Single Driver) ................................................................................ 100