Datasheet

Datasheet
105
Pentium
®
III Xeon™ Processor at 500 and 550 MHz
1 Timing Diagram of Clock Ratio Signals .............................................................. 15
2 Logical Schematic for Clock Ratio Pin Sharing .................................................. 15
3 I-V Curve for nMOS Device ................................................................................ 23
4 BCLK, PICCLK, TCK Generic Clock Waveform ................................................. 29
5 SMBCLK Clock Waveform.................................................................................. 29
6 Valid Delay Timings............................................................................................ 29
7 Setup and Hold Timings ..................................................................................... 30
8 FRC Mode BCLK to PICCLK Timing .................................................................. 30
9 System Bus Reset and Configuration Timings ................................................... 31
10 Power-On Reset and Configuration Timings ...................................................... 31
11 Test Timings (Boundary Scan) ........................................................................... 32
12 Test Reset Timings............................................................................................. 32
13 BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Core Pins ..... 33
14 Low to High AGTL+ Receiver Ringback Tolerance............................................ 34
15 Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback..................... 35
16 Stop Clock State Machine .................................................................................. 38
17 Logical Schematic of SMBus Circuitry................................................................ 40
18 Thermal Plate View............................................................................................. 50
19 Plate Flatness Reference ................................................................................... 51
20 Interface Agent Dispensing Areas and Thermal Plate Temperature Measurement Points53
21 Technique for Measuring T
PLATE
with 0° Angle Attachment .............................. 54
22 Technique for Measuring T
PLATE
with 90° Angle Attachment ............................ 54
23 Guideline Locations for Cover Temperature (T
COVER
) Thermocouple Placement55
24 Isometric View of Pentium
®
III Xeon™ Processor S.E.C. Cartridge................... 56
25 S.E.C. Cartridge Cooling Solution Attach Details (Notes follow Figure 27) ........ 57
26 S.E.C. Cartridge Retention Enabling Details (Notes follow Figure 27)............... 58
27 S.E.C. Cartridge Retention Enabling Details ...................................................... 59
28 Side View of Connector Mating Details .............................................................. 60
29 Top View of Cartridge Insertion Pressure Points................................................ 61
30 Front View of Connector Mating Details ............................................................. 61
31 Boxed Pentium
®
III Xeon™ Processor ............................................................... 71
32 Side View Space Requirements for the Boxed Processor.................................. 72
33 Front View Space Requirements for the Boxed Processor ................................ 73
34 Front Views of the Boxed Processor with Attached Auxiliary Fan (Not Included with Boxed Pro-
cessor)75
35 Front View of Boxed Processor Heatsink with Fan Attach Features (Fan Not Included)75
36 Cross-sectional View of Grommet Attach Features in the Heatsink (Grommet Shown)76
37 Side View Space Recommendation for the Auxiliary Fan .................................. 76
38 Front View Space Recommendations for the Auxiliary Fan ............................... 77
39 Boxed Processor Fan/Heatsink Power Cable Connector Description ................ 77
40 Hardware Components of an ITP ....................................................................... 79
41 AGTL+ Signal Termination ................................................................................. 82
42 TCK with Individual Buffering Scheme ............................................................... 84
43 System Preferred Debug Port Layout................................................................. 85
44 PWRGOOD Relationship at Power-On .............................................................. 94