Intel® 80303 and 80302 I/O Processors Specification Update May 6, 2003 Notice: The Intel® 80303 and Intel® 80302 I/O Processors processor may contain design defects or errors known as errata. Characterized errata that may cause the product’s behavior to deviate from pubished specifications are documented in this specification update.
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Contents Revision History ......................................................................................... 5 Preface....................................................................................................... 7 Summary Table of Changes....................................................................... 8 Identification Information.......................................................................... 14 Errata ........................................................................
This Page Intentionally Left Blank 4 Intel® 80303 and 80302 I/O Processors Specification Update
Revision History Revision History sc Date Version 05/01/03 010 08/27/02 009 11/15/01 008 08/22/01 007 04/24/01 006 04/02/01 005 Description Added Errata 2. Revised Specification Clarifications 4, 7 and 8. Reworded Specification Clarification 4. Added Specification Clarifications 7 and 8. Added Specification Clarifications 5 and 6. Added Document Changes 32 and 33. Added Specification Clarification 4. Added Document Changes 30 and 31. Added Document Changes 25 through 29.
Preface Preface This document is an update to the specifications contained in the Affected Documents/Related Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents.
Summary Table of Changes Summary Table of Changes The following table indicates the errata, specification changes, specification clarifications, or documentation changes which apply to the Intel® 80303 and Intel® 80302 I/O Processors product. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted.
Summary Table of Changes Errata Steppings No. Page Status X 12 NoFix Single-bit and Multi-bit Error Reporting Cannot Be Individually Enabled by ECC Control Register X 12 NoFix Instruction Sequence Can Scoreboard a Register Indefinitely Page Status 14 Doc A-0 A-1 A-2 1 X X 2 X X Errata Specification Changes Steppings No. A-2 1 #-# Specification Changes #-# X Summary of the Intel® 80302 I/O Processor Specification Clarifications Steppings No.
Summary Table of Changes Documentation Changes No.
Identification Information Identification Information Markings Topside Markings GC80303 SSSSSS MALAY FFFFFFFF-[{SN}] INTEL M © ‘2000 Intel® 80303 I/O Processor Die Details Stepping QDF/ Spec Number Voltage (V) Intel® i960® Core Processor Speed (MHz) GC80303 A-0 Q176 3.3 100 Samples - limited testing GC80303 A-0 Q196 3.3 100 Samples - limited testing GC80303 A-1 Q189 3.3 100 Samples - limited testing GC80303 A-1 SL4Q4 3.3 100 Production GC80303 A-2 SL57T 3.
Identification Information Device ID Registers Processor Device ID Register (PDIDR - 0x1710) PCI-to-PCI Bridge Unit Revision ID (RIDR - 0x1008) Address Translation Unit Revision ID Register (ATURID - 0x1208) Intel® i960® Core Processor Device ID (DEVICEID - 0xFF00 8710) 80303 A-0 08879013 0x00 0x00 00823013 80303 A-1 18879013 0x01 0x01 00823013 80303 A-2 18879013 0x01 0x01 00823013 80302 A-2 18878013 0x01 0x01 00823013 Device and Stepping NOTE: There are no functionality difference
Errata Errata 1. Single-bit and Multi-bit Error Reporting Cannot Be Individually Enabled by ECC Control Register Problem: The ECC Control Register ECCR is described as having the ability to select multi-bit error and/or single-bit error reporting (see Table 13-24 on page 13-31 of the Intel® 80303 I/O Processor Developer’s Manual). However, the algorithm does not allow individual enabling; that is, the reporting is either on or off for both multi-bit and single bit error reporting.
Errata Nominally, the emul multiplies two 32-bit operands to produce a long ordinal (64-bit) result stored in two adjacent registers. When the errata occurs, the low-order register receives the correct value, but the high-order register becomes scoreboarded indefinitely. The scoreboarded register is always odd-numbered (i.e., g1, g3, g5, ..., r7, r9, r11, ...) since the emul instruction always directs the high-order result to the odd-numbered register of the destination pair.
Specification Changes Specification Changes 1. Summary of the Intel® 80302 I/O Processor Problem: The Intel® 80302 I/O processor is based on the A-2 stepping of the Intel® 80303 I/O processor. The 80302 I/O processor is identical to the 80303 I/O processor, except the SDRAM and internal bus run at 66 MHz. For applications that use the I2C unit, the I2C clock is generated from the internal bus clock, so the ICCR (I2C Clock Count Register) needs to be properly adjusted.
Specification Clarifications Specification Clarifications 1. ECC is Always Enabled Problem: ECC is always enabled, therefore do not design an Intel® 80303 I/O processor based product without ECC implemented, this causes severe system errors. On the Intel® 80960RM/RN I/O processors, ECCR.3 can be cleared to disable ECC, but with the 80303 I/O processor, ECCR.3 is reserved. 2.
Specification Clarifications 6. SREQ64# Functionality Problem: There is an SREQ64# functionality difference between the A-1 and A-2 steppings of the 80303 I/O processors. (This functionality is also on the 80302 since it is based on the A-2 stepping.) During the power up sequence, the S_REQ64# signal is sampled by PCI devices on the secondary PCI bus to determine 64-bit or 32-bit PCI operation.
Documentation Changes Documentation Changes 1. Title Page revision number Issue: Manual indicates Revision 0.5. Implication: This type of revision numbering is not used with published documents. Refer to the Document Number 272353-001. The extension -001 is the correct revision number for this document. Workaround: Ignore revision number 0.5. Affected Docs: Intel® 80303 I/O Processor Developer’s Manual. 2.
Documentation Changes 3. Figure 13-22 on pg 13-40 did not print correctly Problem: Figure 13-22 on pg 13-40 did not print correctly. Workaround: Replace Figure 13-22 with the following: SCKEout PULLCKE = 1 PULLCKE = 0 P_RST# A6814-01 Affected Docs: Intel® 80303 I/O Processor Developer’s Manual. 4.
Documentation Changes 5. Figure 15-2 on pg 15-3 did not print correctly Problem: Figure 15-2 on pg 15-3 did not print correctly.
Documentation Changes 6. Incorrect Vendor ID in ATU register Problem: The value for the Vendor ID register (ATUVID) is incorrect.
Documentation Changes 8. Table 24-4 on pg 24-8 is incorrect Problem: Table 24-4 on pg 24-8 is incorrect. Workaround: Replace Table 24-4 with the following table: Table 24-4.
Documentation Changes Table 24-4.
Documentation Changes Table 24-4.
Documentation Changes Table 24-4.
Documentation Changes Table 24-4.
Documentation Changes Table 24-4.
Documentation Changes Table 24-4.
Documentation Changes Table 24-4.
Documentation Changes Table 24-4.
Documentation Changes Table 24-4.
Documentation Changes 9. Figure 25-1 on pg 25-1 has incorrect data Problem: The Internal bus in diagram shows 66 MHz bus speed. The actual bus speed is 100 MHz Workaround: Replace Figure 25-1 with the following: Intel® i960® JN CPU 100 MHz 16K I-Cache 4K D-Cache I2C Bus SCL 64-Bit I/F Clock Region 3 DCLK[3:0] DCLKOUT DCLKIN Figure 25-1.
Documentation Changes 11. Figure 25-2 on pg 25-2 did not print correctly Problem: Figure 25-2 on pg 25-2 did not print correctly. Workaround: Replace Figure 25-2 with the following: I_CLK SDQ(71:0) DQ(71:0) SDQ(71:0) DQ(71:0) P_CLK DCLKout CLK(3:0) CLK(3:0) DCLKin SDRAM DIMM0 SDRAM DIMM1 A4662-02 ® Affected Docs: Intel 80303 I/O Processor Developer’s Manual. 12.
Documentation Changes 13. Section 1.2.2 on page 1-2 has incorrect data Problem: The second sentence of the first paragraph is incorrect. It states the Internal Bus operates at 66 MHz. It is actually 100 MHz. Workaround: Change the second sentence to the following: “The Internal Bus operates at 100 MHz and is 64 bits wide.” Affected Docs: Intel® 80303 I/O Processor Developer’s Manual 14. Figure 12-2 on page 12-10 has incorrect data Problem: The Internal bus in diagram shows 66 MHz bus speed.
Documentation Changes 17. Section 13.2.4.3 on page 13-30 has incorrect data Problem: The first sentence incorrectly states, 'If enabled'. ECC is always enabled on the 80303 I/O processor, it is not optional. Workaround: Remove 'If enabled'. Affected Docs: Intel® 80303 I/O Processor Developer’s Manual 18. Figure 15-3 on page 15-7 has missing text Problem: The figure shows 'se_Register + Value of Limit_Register'. It should be 'Base_Register + Value of Limit_Register'.
Documentation Changes 20. Table 8-17 on page 8-38 has incorrect data Problem: The bit locations for External Interrupt 5 are incorrectly shown as bits '9:4'. It should be '7:4'.
Documentation Changes 24. Table 8-15 on page 8-36 needs clarification Problem: ICON.10, Global Interrupt Enable bit, does not state what bit value enables interrupts. Workaround: Add this sentence to the bit description, 'A '0' will globally enable interrupts, and a '1' globally disables interrupts.' Affected Docs: Intel® 80303 I/O Processor Developer’s Manual 25. Table 13-13 on page 13-30 has incorrect data Problem: Syndrome Decoding Error Types and Symptoms are incorrectly stated.
Documentation Changes 26. Section 13.2.4.3, First Paragraph after Table 13-13 has Incorrect Data Problem: First sentence incorrectly states error types for corrected Table 13-13: ...If decoding the syndrome indicates a double-bit or nibble error... Should read as follows: ...”When” decoding the syndrome indicates a “multi”-bit error... Affected Docs: Intel® 80303 I/O Processor Developer’s Manual 27. Section 13.2.4.3, First Paragraph after “Current” Figure 13-16.
Documentation Changes 32. Section 4.5.2 on page 50 is only correct for A-0 and A-1 steppings Problem: The second sentence in Note 7 states, ‘S_REQ64# is deasserted one P_CLK after the deassertion of S_RST#’. This statement is not correct for the A-2 stepping of the 80303 and 80302 I/O processors. Workaround: This statement is only correct for the A-0 and A-1 steppings of the 80303. See Specification Clarification #6 for A-2 stepping functionality.
