Intel Pentium M Processor on 90nm Process with 2-MB L2 Cache Specification Update

Errata
30 Specification Update
Implication: If SMM turns on paging with global paging enabled and then maps any of linear
addresses of SMRAM using global pages, RSM load may load data from the wrong
location.
Workaround: Do not use global pages in system management mode.
Status: For the steppings affected, see the Summary of Tables of Changes.
X39. Using 2M/4M Pages When A20M# Is Asserted May Result in Incorrect
Address Translations
Problem: An external A20M# pin if enabled forces address bit 20 to be masked (forced to zero)
to emulates real-address mode address wraparound at 1 megabyte. However, if all of
the following conditions are met, address bit 20 may not be masked.
• paging is enabled
• a linear address has bit 20 set
• the address references a large page
• A20M# is enabled
Implication: When A20M# is enabled and an address references a large page the resulting
translated physical address may be incorrect. This erratum has not been observed
with any commercially available operating system.
Workaround: Operating systems should not allow A20M# to be enabled if the masking of address
bit 20 could be applied to an address that references a large page. A20M# is normally
only used with the first megabyte of memory.
Status: For the steppings affected, see the Summary of Tables of Changes.
X40. Premature Execution of a Load Operation Prior to Exception Handler
Invocation
Problem: If any of the below circumstances occur it is possible that the load portion of the
instruction will have executed before the exception handler is entered.
1. If an instruction that performs a memory load causes a code segment limit
violation
2. If a waiting floating-point instruction or MMX instruction that performs a memory
load has a floating-point exception pending
3. If an MMX or SSE instruction that performs a memory load and has either
CR0.EM=1 (Emulation bit set), or a floating-point Top-of-Stack (FP TOS) not equal to
0, or a DNA exception pending
Implication: In normal code execution where the target of the load operation is to write back
memory there is no impact from the load being prematurely executed, nor from the
restart and subsequent re-execution of that instruction by the exception handler. If
the target of the load is to uncached memory that has a system side-effect, restarting
the instruction may cause unexpected system behavior due to the repetition of the
side-effect.
Workaround: Code which performs loads from memory that has side-effects can effectively
workaround this behavior by using simple integer-based load instructions when
accessing side-effect memory and by ensuring that all code is written such that a code
segment limit violation cannot occur as a part of reading from side-effect memory.