Intel Pentium M Processor on 90nm Process with 2-MB L2 Cache Specification Update

Errata
24 Specification Update
Status: For the steppings affected, see the Summary of Tables of Changes.
X18. FSTP (Floating Point Store) Instruction Under Certain Conditions May
Result In Erroneously Setting a Valid Bit on an FP (Floating Point)
Stack Register
Problem: An FSTP instruction with a PDE/PTE (Page Directory Entry/Page Table Entry) A/D bit
update followed by user mode access fault due to a code fetch to a page that has
supervisor only access permission may result in erroneously setting a valid bit of an FP
stack register. The FP top of stack pointer is unchanged.
Implication: This erratum may cause an unexpected stack overflow.
Workaround: User mode code should not count on being able to recover from illegal accesses to
memory regions protected with supervisor only access when using FP instructions.
Status: For the steppings affected, see the Summary of Tables of Changes.
X19. An Execute Disable Bit Violation May Occur on a Data Page-Fault
Problem: Under a combination of internal events, unexpected Execute Disable violations may
occur on data accesses that are Execute Disable protected.
Implication: This erratum may cause unexpected Execute Disable violations.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary of Tables of Changes.
X20. CPUID Leaf 0x80000006 May Provide the Incorrect Value for an
8-Way Associative Cache
Problem: CPUID leaf 0x80000006 may return 0x8 in ECX [15:12] to indicate 8-way associative
cache, but the correct encoding for an 8-way associative cache is 0x6.
Implication: This erratum may lead to unexpected system behavior. Intel has only observed this
condition in non-mobile configurations.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary of Tables of Changes.
X21. Snoops during the Execution of a HLT (Halt) Instruction May Lead to
Unexpected System Behavior
Problem: If during the execution of a HLT instruction an external snoop causes an eviction from
the instruction fetch unit (IFU) instruction cache, the processor may, on exit from the
HLT state, erroneously read stale data from the victim cache.
Implication: This erratum may lead to unexpected system behavior. Intel has only observed this
condition in non-mobile configurations.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.