Intel Pentium M Processor on 90nm Process with 2-MB L2 Cache Specification Update

Errata
20 Specification Update
Implication: For RDMSR, undefined values will be read into EDX:EAX. For WRMSR, undefined
processor behavior may result.
Workaround: Do not use invalid MSR addresses with RDMSR or WRMSR.
Status: For the steppings affected, see the Summary of Tables of Changes.
X5. Unable to Disable Reads/Writes to Performance Monitoring Related
MSRs
Problem: The Performance Monitoring Available bit in the miscellaneous processor features MSR
(IA32_MISC_ENABLES.7) was defined so that when it is cleared to a 0, RDMSR/
WRMSR/RDPMC instructions would return all zeros for reads of and prevent any write
to Performance Monitoring related MSRs. Currently it is possible to read from or write
to Performance Monitoring related MSRs when the Performance Monitoring Available
bit is cleared to a 0.
Implication: It is not possible to disallow reads and writes to the Performance Monitoring MSRs.
Intel has not observed this erratum with commercially available software of system.
Workaround: None.
Status: For the steppings affected, see the Summary of Tables of Changes.
X6. Move to Control Register Instruction May Generate a Breakpoint
Report
Problem: A move (MOV) to Control register (CR) instruction where Control register is CR0, CR3
or CR4 may generate a breakpoint report.
Implication: MOV to Control Register Instruction is not expected to generate a breakpoint report.
Workaround: Ignore breakpoint data from MOV to CR instruction.
Status: For the steppings affected, see the Summary of Tables of Changes.
X7. Error in Instruction Fetch Unit (IFU) Can Result in an Erroneous
Machine Check-Exception (#MC)
Problem: A rare combination of events including the generation of a bus lock(s), the execution
of a WBINVD instruction, and a page accessed or dirty bit assist may result in an
erroneous Machine Check-Exception (#MC).
Implication: Due to this erratum, unexpected machine check-exception (#MC) is generated. Intel
has not been able to reproduce this erratum with commercially available software.
Workaround: It is possible for BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary of Tables of Changes.