Intel Pentium M Processor on 90nm Process with 2-MB L2 Cache Specification Update

Summary Tables of Changes
10 Specification Update
AP =
Dual-Core Intel
®
Xeon
®
processor 3000 series
AQ =
Intel
®
Pentium
®
dual-core desktop processor E2000 sequence
AR =
Intel
®
Celeron
®
processor 500 series
AS =
Intel
®
Xeon
®
processor 7200, 7300 series
AV =
Intel
®
Core™2 Extreme processor QX9650 and Intel
®
Core™2 Quad processor Q9000 series
AW =
Intel
®
Core™ 2 Duo processor E8000 series
AX =
Quad-Core Intel
®
Xeon
®
processor 5400 series
AY =
Dual-Core Intel
®
Xeon® processor 5200 series
AZ =
Intel
®
Core™2 Duo Processor and Intel
®
Core™2 Extreme Processor on 45-nm Process
AAA=
Quad-Core Intel
®
Xeon
®
processor 3300 series
AAB=
Dual-Core Intel
®
Xeon
®
E3110 Processor
AAC=
Intel
®
Celeron
®
dual-core processor E1000 series
AAD=
Intel
®
Core™2 Extreme Processor QX9775
Δ
AAE=
Intel
®
Atom™ processor Z5xx series
Δ
Intel processor numbers are not a measure of performance. Processor numbers
differentiate features within each processor family, not across different processor
families. See http://www.intel.com/products/processor_number for details
Note: The specification updates for the Pentium processor, Pentium Pro processor, and other
Intel products do not use this convention.
NO.
B1
C0
Plans
ERRATA
X1
X
X
No Fix
Code Segment (CS) Is Wrong on SMM Handler when SMBASE Is Not
Aligned
X2
X
X
No Fix
IFU/BSU Deadlock May Cause System Hang
X3
X
X
No Fix
Memory Aliasing with Inconsistent A and D Bits May Cause Processor
Deadlock
X4
X
X
No Fix
RDMSR or WRMSR to Invalid MSR Address May Not Cause GP Fault
X5
X
X
No Fix
Unable To Disable Reads/Writes to Performance Monitoring Related
MSRs
X6
X
X
No Fix
Move to Control Register Instruction May Generate a Breakpoint
Report
X7
X
X
No Fix
Error in Instruction Fetch Unit (IFU) Can Result in an Erroneous
Machine Check-Exception (#MC)
X8
X
X
No Fix
Code Fetch Matching Disabled Debug Register May Cause Debug
Exception
X9
X
X
No Fix
Upper Four PAT Entries Not Usable with Mode B or Mode C Paging
X10
X
X
No Fix
SSE/SSE2 Streaming Store Resulting in a Self-Modifying Code (SMC)
Event May Cause Unexpected Behavior
X11
X
X
No Fix
Code Segment Limit Violation May Occur on 4 Gigabyte Limit Check
X12
X
X
No Fix
FST Instruction with Numeric and Null Segment Exceptions may
cause General Protection Faults to be Missed and FP Linear Address
(FLA) Mismatch