Intel Pentium M Processor on 90nm Process with 2-MB L2 Cache Specification Update

Errata
Specification Update 29
Problem: STPCLK# is asserted to enable the processor to enter a low-power state. Under some
circumstances, when STPCLK# becomes active, a pending BTS (Branch Trace Store)
message may be either lost and not written or written with corrupted branch address
to the Debug Store area.
Implication: BTS messages may be lost in the presence of STPCLK# assertions.
Workaround: None identified.
Status: For the steppings affected, see the Summary of Tables of Changes.
X36. Last Exception Record (LER) MSRs May Be Incorrectly Updated
Problem: The LASTINTTOIP and LASTINTFROMIP MSRs (1DDH-1DEH) may contain incorrect
values after the following events: masked SSE2 floating-point exception, StopClk, NMI
and INT.
Implication: The value of the LER MSR may be incorrectly updated to point to a SIMD Floating-
Point instruction even though no exception occurred on that instruction or to point to
an instruction that was preceded by a StopClk interrupt or rarely not to be updated on
Interrupts (NMI and INT).
Workaround: None identified.
Status: For the steppings affected, see the Summary of Tables of Changes.
X37. Writing the Local Vector Table (LVT) When an Interrupt Is Pending
May Cause an Unexpected Interrupt
Problem: If a local interrupt is pending when the LVT entry is written, an interrupt may be taken
on the new interrupt vector even if the mask bit is set.
Implication: An interrupt may immediately be generated with the new vector when a LVT entry is
written, even if the new LVT entry has the mask bit set. If there is no Interrupt
Service Routine (ISR) set up for that vector the system will GP fault. If the ISR does
not do an End of Interrupt (EOI) the bit for the vector will be left set in the in-service
register and mask all interrupts at the same or lower priority.
Workaround: Any vector programmed into an LVT entry must have an ISR associated with it, even if
that vector was programmed as masked. This ISR routine must do an EOI to clear any
unexpected interrupts that may occur. The ISR associated with the spurious vector
does not generate an EOI, therefore the spurious vector should not be used when
writing the LVT.
Status: For the steppings affected, see the Summary of Tables of Changes.
X38. Global Pages in the Data Translation Look-Aside Buffer (DTLB) May
Not Be Flushed by RSM instruction before Restoring the Architectural
State from SMRAM
Problem: The Resume from System Management Mode (RSM) instruction does not flush global
pages from the Data Translation Look-Aside Buffer (DTLB) prior to reloading the saved
architectural state.