Intel Pentium M Processor on 90nm Process with 2-MB L2 Cache Specification Update

Errata
Specification Update 27
X28. DR3 Address Match on MOVD/MOVQ/MOVNTQ Memory Store
Instruction May Incorrectly Increment Performance Monitoring Count
for Saturating SIMD Instructions Executed (Event B1h)
Problem: Performance monitoring for Event B1h normally increments on saturating SIMD
instruction executed. Regardless of DR7 programming, if the linear address of a
memory store MOVD/MOVQ/MOVNTQ instruction executed matches the address in
DR3, the B1h counter may be incorrectly incremented.
Implication: The value observed for performance monitoring count for saturating SIMD instructions
executed may be too high.
Workaround: None identified.
Status: For the steppings affected, see the Summary of Tables of Changes.
X29. Pending x87 FPU Exceptions (#MF) Following STI May Be Serviced
before Higher Priority Interrupts
Problem: Interrupts that are pending prior to the execution of the STI (Set Interrupt Flag)
instruction are normally serviced immediately after the instruction following the STI.
An exception to this is if the following instruction triggers a #MF. In this situation, the
interrupt should be serviced before the #MF. Because of this erratum, if following STI,
an instruction that triggers a #MF is executed while STPCLK#, Enhanced Intel
®
SpeedStep Technology transitions or Thermal Monitor events occur, the pending #MF
may be serviced before higher priority interrupts.
Implication: Software may observe #MF being serviced before higher priority interrupts.
Workaround: None identified.
Status: For the steppings affected, see the Summary of Tables of Changes.
X30. Processor INIT# Will Cause a System Hang if Triggered during an NMI
Interrupt Routine Performed during Shutdown
Problem: During the execution of an NMI interrupt handler, if shutdown occurs followed by the
INIT# signal being triggered, the processor will attempt initialization but fail soft
reset.
Implication: Due to this erratum the system may hang.
Workaround: None identified.
Status: For the steppings affected, see the Summary of Tables of Changes.
X31. Certain Performance Monitoring Counters Related to Bus, L2 Cache
and Power Management Are Inaccurate
Problem: All Performance Monitoring Counters in the ranges 21H-3DH and 60H-7FH may have
inaccurate results up to ±7.
Implication: There may be a small error in the affected counts.