Intel Pentium M Processor on 90nm Process with 2-MB L2 Cache Specification Update

Errata
Specification Update 25
Status: For the steppings affected, see the Summary of Tables of Changes.
X22. Invalid Entries in Page-Directory-Pointer-Table-Register (PDPTR) May
Cause General Protection (#GP) Exception If the Reserved Bits are
Set to One
Problem: Invalid entries in Page-Directory-Pointer-Table-Register (PDPTR) that have the
reserved bits set to one, may cause a General Protection (#GP) exception.
Implication: Intel has not observed this erratum with any commercially available software.
Workaround: Do not set the reserved bits to one when PDPTR entries are invalid.
Status: For the steppings affected, see the Summary of Tables of Changes.
X23. INIT Does Not Clear Global Entries in the TLB
Problem: INIT may not flush a TLB entry when:
1. The processor is in protected mode with paging enabled and the page global
enable flag is set (PGE bit of CR4 register)
2. G bit for the page table entry is set
3. TLB entry is present in TLB when INIT occurs
Implication: Software may encounter unexpected page fault or incorrect address translation due to
a TLB entry erroneously left in TLB after INIT.
Workaround: Write to CR3, CR4 (setting bits PSE, PGE or PAE) or CR0 (setting bits PG or PE)
registers before writing to memory early in BIOS code to clear all the global entries
from TLB.
Status: For the steppings affected, see the Summary of Tables of Changes.
X24. Use of Memory Aliasing with Inconsistent Memory Type May Cause a
System Hang or a Machine Check Exception
Problem: Software that implements memory aliasing by having more than one linear addresses
mapped to the same physical page with different cache types may cause the system
to hang or to report a machine check exception (MCE). This would occur if one of the
addresses is non-cacheable and used in code segment and the other a cacheable
address. If the cacheable address finds its way in instruction cache, and non-
cacheable address is fetched in IFU, the processor may invalidate the non-cacheable
address from the fetch unit. Any micro-architectural event that causes instruction
restart will expect this instruction to still be in fetch unit and lack of it will cause
system hang or a MCE.
Implication: This erratum has not been observed with commercially available software.
Workaround: Although it is possible to have a single physical page mapped by two different linear
addresses with different memory types, Intel has strongly discouraged this practice as
it may lead to undefined results. Software that needs to implement memory aliasing
should manage the memory type consistency.
Status: For the steppings affected, see the Summary of Tables of Changes.