Intel Pentium M Processor on 90nm Process with 2-MB L2 Cache Specification Update

Errata
22 Specification Update
Implication: Due to this erratum, any of the following events may occur:
1. A data access break point may be incorrectly reported on the instruction pointer
(IP) just before the store instruction.
2. A non-cacheable store can appear twice on the external bus (the first time it will
write only 8 bytes, the second time it will write the entire 16 bytes).
Intel has not observed this erratum with any commercially available software. This
erratum has been seen in a synthetic test environment.
Workaround: None.
Status: For the steppings affected, see the Summary of Tables of Changes.
X11. Code Segment Limit Violation May Occur on 4 Gigabyte Limit Check
Problem: Code Segment limit violation may occur on 4 Gigabyte limit check when the code
stream wraps around in a way that one instruction ends at the last byte of the
segment and the next instruction begins at 0x0.
Implication: This is a rare condition that may result in a system hang. Intel has not observed this
erratum with any commercially available software, or system.
Workaround: Avoid code that wraps around segment limit.
Status: For the steppings affected, see the Summary of Tables of Changes.
X12. FST Instruction with Numeric and Null Segment Exceptions May Cause
General Protection Faults to Be Missed and FP Linear Address (FLA)
Mismatch
Problem: FST instruction combined with numeric and null segment exceptions may cause
General Protection Faults to be missed and FP Linear Address (FLA) mismatch.
Implication: This is a rare condition that may result in a system hang. Intel has not observed this
erratum with any commercially available software, or system.
Workaround: None identified.
Status: For the steppings affected, see the Summary of Tables of Changes.
X13. Removed; See Erratum X1.
X14. Page with PAT (Page Attribute Table) Set to USWC (Uncacheable
Speculative Write Combine) While Associated MTRR (Memory Type
Range Register) Is UC (Uncacheable) May Consolidate to UC
Problem: A page whose PAT memory type is USWC while the relevant MTRR memory type is UC,
the consolidated memory type may be treated as UC (rather than WC as specified in
IA-32 Intel
®
Architecture Software Developer's Manual).
Implication: When this erratum occurs, the memory page may be as UC (rather than WC). This
may have a negative performance impact.