Intel Pentium M Processor on 90nm Process with 2-MB L2 Cache Specification Update

Errata
Specification Update 19
Errata
X1. Code Segment (CS) Is Wrong on SMM Handler When SMBASE Is Not
Aligned
Problem: With SMBASE being relocated to a non-aligned address, during SMM entry the CS can
be improperly updated, which can lead to an incorrect SMM handler.
Implication: This is a rare condition that may result in a system hang. Intel has not observed this
erratum with any commercially available software or system.
Workaround: Align SMBASE to 32 KB.
Status: For the steppings affected, see the Summary of Tables of Changes.
X2. IFU/BSU Deadlock May Cause System Hang
Problem: A lockable instruction with memory operand that spans across two pages may, given
some rare internal conditions, hang the system.
Implication: When this erratum occurs, the system may hang. Intel has not observed this erratum
with any commercially available software or system.
Workaround: Lockable data should always be contained in a single page.
Status: For the steppings affected, see the Summary of Tables of Changes.
X3. Memory Aliasing with Inconsistent A and D Bits May Cause Processor
Deadlock
Problem: In the event that software implements memory aliasing by having two page directory
entries (PDEs) point to a common page table entry (PTE) and the Accessed and Dirty
bits for the two PDEs are allowed to become inconsistent the processor may become
deadlocked.
Implication: This erratum has not been observed with commercially available software.
Workaround: Software that needs to implement memory aliasing in this way should manage the
consistency of the Accessed and Dirty bits.
Status: For the steppings affected, see the Summary of Tables of Changes.
X4. RDMSR or WRMSR to Invalid MSR Address May Not Cause GP Fault
Problem: The RDMSR and WRMSR instructions allow reading or writing of MSR’s ( Model Specific
Registers) based on the index number placed in ECX. The processor should reject
access to any reserved or unimplemented MSRs by generating #GP(0). However,
there are some invalid MSR addressers for which the processor will not generate
#GP(0). This erratum has not been observed with commercially available software.