Intel Pentium M Processor on 90nm Process with 2-MB L2 Cache Specification Update
Summary Tables of Changes
12 Specification Update
NO.
B1
C0
Plans
ERRATA
X33
X
X
No Fix
A Write to an APIC Register Sometimes May Appear to Have Not
Occurred
X34
X
X
No Fix
The Processor May Report a #TS Instead of a #GP Fault
X35
X
X
No Fix
BTS Message May Be Lost When the STPCLK# Signal Is Active
X36
X
X
No Fix
Last Exception Record (LER) MSRs May Be Incorrectly Updated
X37
X
X
No Fix
Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause
an Unexpected Interrupt
X38
X
X
No Fix
Global Pages in the Data Translation Look-Aside Buffer (DTLB) May
Not Be Flushed by RSM Iinstruction before Restoring the
Architectural State from SMRAM
X39
X
X
No Fix
Using 2M/4M pages When A20M# Is Asserted May Result in Incorrect
Address Translations
X40
X
X
No Fix
Premature Execution of a Load Operation Prior to Exception Handler
Invocation
X41
X
X
No Fix
#GP Fault Is NOT Generated on Writing IA32_MISC_ENABLE [34]
When Execute Disable (XD) Is Not Supported
X42
X
X
No Fix
SSE/SSE2 Streaming Store Resulting in a Self-Modifying Code (SMC)
Event May Cause Unexpected Behavior
X43
X
X
No Fix
Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR
Image Leads to Partial Memory Update
X44
X
X
No Fix
Values for LBR/BTS/BTM Will Be Incorrect after an Exit from SMM
X45
X
X
No Fix
The BS Flag in DR6 May Be Set for Non-Single-Step #DB Exception
X46
X
X
No Fix
BTM/BTS Branch-From Instruction Address May Be
Incorrect for Software Interrupts
X47
X
X
No Fix
Fault on ENTER Instruction May Result in Unexpected Values on
Stack Frame
X48
X
X
No Fix
Unaligned Accesses to Paging Structures May Cause the Processor to
Hang
X49
X
X
No Fix
INVLPG Operation for Large (2M/4M) Pages May be Incomplete
under Certain Conditions
X50
X
X
No Fix
Page Access Bit May be Set Prior to Signaling a Code Segment Limit
Fault
X51
X
X
No Fix
EFLAGS, CR0, CR4 and the EXF4 Signal May be Incorrect after
Shutdown
X52
X
X
No Fix
Store Ordering May be Incorrect between WC and WP Memory Types
X53
X
X
No Fix
Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not
Count Some Transitions
X54
X
X
No Fix
An Enabled Debug Breakpoint or Single Step Trap May Be Taken
after MOV SS/POP SS Instruction if it is Followed by an Instruction
That Signals a Floating Point Exception
X55
X
X
No Fix
Corruption of CS Segment Register During RSM While Transitioning From
Real Mode to Protected Mode