Intel Pentium M Processor Datasheet

14 Intel
®
Pentium
®
M Processor Datasheet
Low Power Features
— If the target frequency is higher than the current frequency, Vcc is ramped up by placing a
new value on the VID pins and the PLL then locks to the new frequency.
— If the target frequency is lower than the current frequency, the PLL locks to the new
frequency and the Vcc is changed through the VID pin mechanism.
— Software transitions are accepted at any time. If a previous transition is in progress, the
new transition is deferred until its completion.
• The processor controls voltage ramp rates internally to ensure glitch free transitions.
• Low transition latency and large number of transitions possible per second.
— Processor core (including L2 cache) is unavailable for up to 10 µs during the frequency
transition
— The bus protocol (BNR# mechanism) is used to block snooping
• No bus master arbiter disable required prior to transition and no processor cache flush
necessary.
• Improved Intel Thermal Monitor mode.
— When the on-die thermal sensor indicates that the die temperature is too high, the
processor can automatically perform a transition to a lower frequency/voltage specified in
a software programmable MSR.
— The processor waits for a fixed time period. If the die temperature is down to acceptable
levels, an up transition to the previous frequency/voltage point occurs.
— An interrupt is generated for the up and down Intel Thermal Monitor transitions enabling
better system level thermal management.
2.3 Processor System Bus Low Power Enhancements
The Intel Pentium M processor incorporates the following processor system bus low power
enhancements:
• Dynamic FSB power down
• BPRI# control for address and control input buffers
• Dynamic on-die termination disabling
• Low VCCP (I/O termination voltage)
The Intel Pentium M processor incorporates the DPWR# signal that controls the Data Bus input
buffers on the processor. The DPWR# signal disables the buffers when not used and activates them
only when data bus activity occurs, resulting in significant power savings with no performance
impact. BPRI# control also allows the processor address and control input buffers to be turned off
when the BPRI# signal is inactive. The On Die Termination on the processor PSB buffers is
disabled when the signals are driven low, resulting in additional power savings. The low I/O
termination voltage is on a dedicated voltage plane independent of the core voltage, enabling low I/
O switching power at all times.