Guide

System Memory Design Guidelines (DDR-SDRAM)
R
94 Intel
®
852GM Chipset Platform Design Guide
7.3.4.2. SDQS to Clock Length Matching Requirements
The first step in length matching is to determine the SDQS length range based on the SCK/SCK#
reference length defined previously. The total length of the SDQS strobe signals, including package
length, between the GMCH die-pad and the SO-DIMMs must fall within the range defined in the
formulas below. See the clock Section for the definition of the clock reference length. Refer to Figure
46 for the definition of the various trace segments. The length tuning requirements are also depicted in
Figure 47. Refer to Section 7.1 for more details on length matching and length formula requirements.
Length range formula for SO-DIMM0:
X
0
= SCK/SCLK#[1:0] total reference length, including package length. See clock Section 7.3.1.
Y
0
= SDQS[7:0] total length = GMCH package + L1 + L2, as shown in Figure 47,
where: ( X
0
– 1.0” ) ≤ Y
0
≤ ( X
0
+ 0.5” )
Length range formula for SO-DIMM1:
X
1
= SCK/SCK#[4:3] total reference length, including package length. See clock Section 7.3.1
Y
1
= SDQS[7:0] total length = GMCH package + L1 + L2 + L3, as shown Figure 47,
where: ( X
1
– 1.0” ) ≤ Y
1
≤ ( X
1
+ 0.5” )
Length matching is only performed from the GMCH to the SO-DIMMs and does not involve the length
of L4, which can vary over its entire range. Intel recommends that routing segment length L3 between
SO-DIMM0 to SO-DIMM1 be held fairly constant and equal to the offset between clock reference
lengths X0 and X1. This will produce the most straightforward length matching scenario. Note that a
nominal SDQS package length of 750 mils can be used to estimate MB lengths prior to performing
package length compensation. Refer to Section 7.2 for more details on package length compensation.